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| author | Erlang/OTP <[email protected]> | 2017-08-25 09:35:57 +0200 |
|---|---|---|
| committer | Erlang/OTP <[email protected]> | 2017-08-25 09:35:57 +0200 |
| commit | 8af27d1ffdda3e061ebc21eaa22ee8e49372e6b5 (patch) | |
| tree | d6f2b9612e12d9351e982b195a5381d100002dd8 /erts/emulator | |
| parent | f58abbbb6e3f50e76b7a355b0f1b062cb30b8d3a (diff) | |
| parent | 076167bae6cc57d188cdf59fd94c82f3a36ee7ee (diff) | |
| download | otp-8af27d1ffdda3e061ebc21eaa22ee8e49372e6b5.tar.gz otp-8af27d1ffdda3e061ebc21eaa22ee8e49372e6b5.tar.bz2 otp-8af27d1ffdda3e061ebc21eaa22ee8e49372e6b5.zip | |
Merge branch 'rickard/timer-sid-bug/OTP-14548' into maint-20
* rickard/timer-sid-bug/OTP-14548:
Fix scheduler id field in timers
# Conflicts:
# erts/emulator/beam/erl_hl_timer.c
Diffstat (limited to 'erts/emulator')
| -rw-r--r-- | erts/emulator/beam/erl_hl_timer.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/erts/emulator/beam/erl_hl_timer.c b/erts/emulator/beam/erl_hl_timer.c index 99995be464..af1cc6b933 100644 --- a/erts/emulator/beam/erl_hl_timer.c +++ b/erts/emulator/beam/erl_hl_timer.c @@ -103,14 +103,14 @@ typedef enum { # define ERTS_HLT_SMP_MEMBAR_LoadLoad_LoadStore #endif -/* Bit 0 to 9 contains scheduler id (see mask below) */ -#define ERTS_TMR_ROFLG_HLT (((Uint32) 1) << 10) -#define ERTS_TMR_ROFLG_BIF_TMR (((Uint32) 1) << 11) -#define ERTS_TMR_ROFLG_PRE_ALC (((Uint32) 1) << 12) -#define ERTS_TMR_ROFLG_REG_NAME (((Uint32) 1) << 13) -#define ERTS_TMR_ROFLG_PROC (((Uint32) 1) << 14) -#define ERTS_TMR_ROFLG_PORT (((Uint32) 1) << 15) -#define ERTS_TMR_ROFLG_CALLBACK (((Uint32) 1) << 16) +/* Bit 0 to 10 contains scheduler id (see mask below) */ +#define ERTS_TMR_ROFLG_HLT (((Uint32) 1) << 11) +#define ERTS_TMR_ROFLG_BIF_TMR (((Uint32) 1) << 12) +#define ERTS_TMR_ROFLG_PRE_ALC (((Uint32) 1) << 13) +#define ERTS_TMR_ROFLG_REG_NAME (((Uint32) 1) << 14) +#define ERTS_TMR_ROFLG_PROC (((Uint32) 1) << 15) +#define ERTS_TMR_ROFLG_PORT (((Uint32) 1) << 16) +#define ERTS_TMR_ROFLG_CALLBACK (((Uint32) 1) << 17) #define ERTS_TMR_ROFLG_SID_MASK \ (ERTS_TMR_ROFLG_HLT - (Uint32) 1) |