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author | Rickard Green <[email protected]> | 2010-08-10 13:42:42 +0200 |
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committer | Rickard Green <[email protected]> | 2010-08-10 13:42:42 +0200 |
commit | 59ee2a593090e7d53c97ceba63cbd300d1b9657e (patch) | |
tree | b60c1078eebb64955bba181cfc118ee2f3b845d4 /erts/include/internal/sparc32/atomic.h | |
parent | 0d553b45b5c3ae8287340887f271bc70f1f1370c (diff) | |
parent | 300b419486c1ca88e33938f182d5d5a8b90fb73f (diff) | |
download | otp-59ee2a593090e7d53c97ceba63cbd300d1b9657e.tar.gz otp-59ee2a593090e7d53c97ceba63cbd300d1b9657e.tar.bz2 otp-59ee2a593090e7d53c97ceba63cbd300d1b9657e.zip |
Merge branch 'rickard/ethread-rewrite/OTP-8544' into dev
* rickard/ethread-rewrite/OTP-8544:
Rewrite ethread library
Diffstat (limited to 'erts/include/internal/sparc32/atomic.h')
-rw-r--r-- | erts/include/internal/sparc32/atomic.h | 39 |
1 files changed, 38 insertions, 1 deletions
diff --git a/erts/include/internal/sparc32/atomic.h b/erts/include/internal/sparc32/atomic.h index 8fde449a52..2a995d4465 100644 --- a/erts/include/internal/sparc32/atomic.h +++ b/erts/include/internal/sparc32/atomic.h @@ -32,7 +32,7 @@ typedef struct { __asm__ __volatile__("membar #LoadLoad|#LoadStore|#StoreLoad|#StoreStore\n" \ : : : "memory") -#ifdef ETHR_TRY_INLINE_FUNCS +#if defined(ETHR_TRY_INLINE_FUNCS) || defined(ETHR_AUX_IMPL__) #if defined(__arch64__) #define CASX "casx" @@ -172,6 +172,43 @@ ethr_native_atomic_cmpxchg(ethr_native_atomic_t *var, long new, long old) return new; } +/* + * Atomic ops with at least specified barriers. + */ + +static ETHR_INLINE long +ethr_native_atomic_read_acqb(ethr_native_atomic_t *var) +{ + long res = ethr_native_atomic_read(var); + __asm__ __volatile__("membar #StoreLoad|#StoreStore"); + return res; +} + +static ETHR_INLINE void +ethr_native_atomic_set_relb(ethr_native_atomic_t *var, long i) +{ + __asm__ __volatile__("membar #LoadStore|#StoreStore"); + ethr_native_atomic_set(var, i); +} + +static ETHR_INLINE void +ethr_native_atomic_dec_relb(ethr_native_atomic_t *var) +{ + __asm__ __volatile__("membar #LoadStore|#StoreStore"); + ethr_native_atomic_dec(var); +} + +static ETHR_INLINE long +ethr_native_atomic_dec_return_relb(ethr_native_atomic_t *var) +{ + __asm__ __volatile__("membar #LoadStore|#StoreStore"); + return ethr_native_atomic_dec_return(var); +} + +#define ethr_native_atomic_inc_return_acqb ethr_native_atomic_inc_return +#define ethr_native_atomic_cmpxchg_acqb ethr_native_atomic_cmpxchg +#define ethr_native_atomic_cmpxchg_relb ethr_native_atomic_cmpxchg + #endif /* ETHR_TRY_INLINE_FUNCS */ #endif /* ETHR_SPARC32_ATOMIC_H */ |