From 38c10d20f7b0a83f4d94a92d30ca649b86b0a7cb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Magnus=20L=C3=A5ng?= <margnus1@telia.com>
Date: Mon, 20 Jun 2016 18:26:39 +0200
Subject: hipe_x86: Add code rewrite RA callbacks

These will not only be useful for hipe_regalloc_prepass, but also, after
the introduction of a mk_move/2 (or similar) callback, for the purpose
of range splitting.

Since the substitution needed to case over all the instructions, a new
module, hipe_x86_subst, was introduced to the x86 backend.

Due to differences in the 'jtab' field of a #jmp_switch{} between x86
and amd64, it regrettably needed to be duplicated to hipe_amd64_subst.
---
 lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | 26 ++++++++++++++++++++++++
 lib/hipe/regalloc/hipe_x86_specific.erl        | 28 ++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

(limited to 'lib/hipe/regalloc')

diff --git a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl
index 35d19ef1df..dec7c1734d 100644
--- a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl
+++ b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl
@@ -57,6 +57,12 @@
 -export([check_and_rewrite/2,
 	 check_and_rewrite/3]).
 
+%% callbacks for hipe_regalloc_prepass
+-export([new_reg_nr/0,
+	 update_reg_nr/2,
+	 update_bb/3,
+	 subst_temps/2]).
+
 %%----------------------------------------------------------------------------
 
 -include("../flow/cfg.hrl").
@@ -150,6 +156,9 @@ number_of_temporaries(_CFG) ->
 bb(CFG, L) ->
   hipe_x86_cfg:bb(CFG, L).
 
+update_bb(CFG,L,BB) ->
+  hipe_x86_cfg:bb_add(CFG,L,BB).
+
 %% AMD64 stuff
 
 def_use(Instruction) ->
@@ -186,6 +195,23 @@ is_move(Instruction) ->
 reg_nr(Reg) ->
   hipe_x86:temp_reg(Reg).
 
+new_reg_nr() ->
+  hipe_gensym:get_next_var(x86).
+
+update_reg_nr(Nr, _Temp) ->
+  hipe_x86:mk_temp(Nr, 'double').
+
+subst_temps(SubstFun, Instr) ->
+  hipe_amd64_subst:insn_temps(
+    fun(Op) ->
+	case hipe_x86:temp_is_allocatable(Op)
+	  andalso hipe_x86:temp_type(Op) =:= 'double'
+	of
+	  true -> SubstFun(Op);
+	  false -> Op
+	end
+    end, Instr).
+
 -spec new_spill_index(non_neg_integer()) -> pos_integer().
 new_spill_index(SpillIndex) when is_integer(SpillIndex) ->
   SpillIndex + 1.
diff --git a/lib/hipe/regalloc/hipe_x86_specific.erl b/lib/hipe/regalloc/hipe_x86_specific.erl
index d5acdc0bd5..627aaa19b4 100644
--- a/lib/hipe/regalloc/hipe_x86_specific.erl
+++ b/lib/hipe/regalloc/hipe_x86_specific.erl
@@ -25,12 +25,14 @@
 -define(HIPE_X86_REGISTERS, hipe_amd64_registers).
 -define(HIPE_X86_LIVENESS, hipe_amd64_liveness).
 -define(HIPE_X86_DEFUSE, hipe_amd64_defuse).
+-define(HIPE_X86_SUBST, hipe_amd64_subst).
 -else.
 -define(HIPE_X86_SPECIFIC, hipe_x86_specific).
 -define(HIPE_X86_RA_POSTCONDITIONS, hipe_x86_ra_postconditions).
 -define(HIPE_X86_REGISTERS, hipe_x86_registers).
 -define(HIPE_X86_LIVENESS, hipe_x86_liveness).
 -define(HIPE_X86_DEFUSE, hipe_x86_defuse).
+-define(HIPE_X86_SUBST, hipe_x86_subst).
 -endif.
 
 -module(?HIPE_X86_SPECIFIC).
@@ -68,6 +70,12 @@
 %% callbacks for hipe_regalloc_loop
 -export([check_and_rewrite/2]).
 
+%% callbacks for hipe_regalloc_prepass
+-export([new_reg_nr/0,
+	 update_reg_nr/2,
+	 update_bb/3,
+	 subst_temps/2]).
+
 check_and_rewrite(CFG, Coloring) ->
   ?HIPE_X86_RA_POSTCONDITIONS:check_and_rewrite(CFG, Coloring, 'normal').
 
@@ -152,6 +160,9 @@ number_of_temporaries(_CFG) ->
 bb(CFG,L) ->
   hipe_x86_cfg:bb(CFG,L).
 
+update_bb(CFG,L,BB) ->
+  hipe_x86_cfg:bb_add(CFG,L,BB).
+
 %% X86 stuff
 
 def_use(Instruction) ->
@@ -199,5 +210,22 @@ is_move(Instruction) ->
 reg_nr(Reg) ->
   hipe_x86:temp_reg(Reg).
 
+new_reg_nr() ->
+  hipe_gensym:get_next_var(x86).
+
+update_reg_nr(Nr, Temp) ->
+  hipe_x86:mk_temp(Nr, hipe_x86:temp_type(Temp)).
+
+subst_temps(SubstFun, Instr) ->
+  ?HIPE_X86_SUBST:insn_temps(
+    fun(Op) ->
+	case hipe_x86:temp_is_allocatable(Op)
+	  andalso hipe_x86:temp_type(Op) =/= 'double'
+	of
+	  true -> SubstFun(Op);
+	  false -> Op
+	end
+    end, Instr).
+
 new_spill_index(SpillIndex) when is_integer(SpillIndex) ->
   SpillIndex+1.
-- 
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