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authorRickard Green <[email protected]>2016-02-09 18:23:26 +0100
committerRickard Green <[email protected]>2016-02-09 20:54:03 +0100
commitfd7fa4606406de960366db4c5d8cb924e25dddb5 (patch)
tree9e4869f4db029d84fb84edc0a3b3e40479ada1cd
parentd96471b3f404f7341279d8598dd74d92fb1a923c (diff)
downloadotp-gcc-5-pic-cmpxchg8b-quickfix.tar.gz
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Quickfix for cmpxchg8b inline asm when pic and gcc >= 5.0 is usedgcc-5-pic-cmpxchg8b-quickfix
-rw-r--r--erts/include/internal/i386/ethr_dw_atomic.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/erts/include/internal/i386/ethr_dw_atomic.h b/erts/include/internal/i386/ethr_dw_atomic.h
index e8c4119ef0..caba633981 100644
--- a/erts/include/internal/i386/ethr_dw_atomic.h
+++ b/erts/include/internal/i386/ethr_dw_atomic.h
@@ -115,6 +115,8 @@ ethr_native_dw_atomic_addr(ethr_native_dw_atomic_t *var)
return (ethr_sint_t *) ETHR_DW_NATMC_MEM__(var);
}
+#if !ETHR_AT_LEAST_GCC_VSN__(5, 0, 0)
+
#if ETHR_SIZEOF_PTR == 4 && defined(__PIC__) && __PIC__
/*
* When position independent code is used in 32-bit mode, the EBX register
@@ -138,6 +140,7 @@ ethr_native_dw_atomic_addr(ethr_native_dw_atomic_t *var)
# endif
#endif
+#endif /* < gcc-5.0 */
#define ETHR_HAVE_ETHR_NATIVE_DW_ATOMIC_CMPXCHG_MB