hipe_ppc: Add code rewrite RA callbacks

These will not only be useful for hipe_regalloc_prepass, but also, after
the introduction of a mk_move/2 (or similar) callback, for the purpose
of range splitting.

Since the substitution needed to case over all the instructions, a new
module, hipe_ppc_subst, was introduced to the ppc backend.

5 files changed, 136 insertions, 0 deletions

diff --git a/lib/hipe/main/hipe.app.src b/lib/hipe/main/hipe.app.src
index d1d98c930d..96bcf7d7e8 100644
--- a/lib/hipe/main/hipe.app.src
+++ b/lib/hipe/main/hipe.app.src
@@ -144,6 +144,7 @@
 	     hipe_ppc_registers,
 	     hipe_ppc_specific,
 	     hipe_ppc_specific_fp,
+	     hipe_ppc_subst,
 	     hipe_profile,
 	     hipe_reg_worklists,
 	     hipe_regalloc_loop,
diff --git a/lib/hipe/ppc/Makefile b/lib/hipe/ppc/Makefile
index 1901dfa671..1ca1d51846 100644
--- a/lib/hipe/ppc/Makefile
+++ b/lib/hipe/ppc/Makefile
@@ -63,6 +63,7 @@ MODULES=hipe_ppc \
 	hipe_ppc_ra_postconditions \
 	hipe_ppc_ra_postconditions_fp \
 	hipe_ppc_registers \
+	hipe_ppc_subst \
 	hipe_rtl_to_ppc
 
 HRL_FILES=hipe_ppc.hrl
diff --git a/lib/hipe/ppc/hipe_ppc_subst.erl b/lib/hipe/ppc/hipe_ppc_subst.erl
new file mode 100644
index 0000000000..5e43fd6471
--- /dev/null
+++ b/lib/hipe/ppc/hipe_ppc_subst.erl
@@ -0,0 +1,82 @@
+%% -*- erlang-indent-level: 2 -*-
+%%
+%% %CopyrightBegin%
+%% 
+%% Copyright Ericsson AB 2016. All Rights Reserved.
+%% 
+%% Licensed under the Apache License, Version 2.0 (the "License");
+%% you may not use this file except in compliance with the License.
+%% You may obtain a copy of the License at
+%%
+%%     http://www.apache.org/licenses/LICENSE-2.0
+%%
+%% Unless required by applicable law or agreed to in writing, software
+%% distributed under the License is distributed on an "AS IS" BASIS,
+%% WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+%% See the License for the specific language governing permissions and
+%% limitations under the License.
+%% 
+%% %CopyrightEnd%
+%%
+
+-module(hipe_ppc_subst).
+-export([insn_temps/2]).
+-include("hipe_ppc.hrl").
+
+%% These should be moved to hipe_ppc and exported
+-type temp()    :: #ppc_temp{}.
+-type oper()    :: temp() | #ppc_simm16{} | #ppc_uimm16{}.
+-type arg()     :: temp() | integer().
+-type insn()    :: tuple(). % for now
+
+-type subst_fun() :: fun((temp()) -> temp()).
+
+%% @doc Maps over the temporaries in an instruction
+-spec insn_temps(subst_fun(), insn()) -> insn().
+insn_temps(T, I) ->
+  A = fun(O) -> arg_temps(T, O) end,
+  O = fun(O) -> oper_temps(T, O) end,
+  case I of
+      #alu{dst=D,src1=L,src2=R} -> I#alu{dst=T(D),src1=T(L),src2=O(R)};
+      #b_label{} -> I;
+      %% #bc{} -> I;
+      #bctr{} -> I;
+      #blr{} -> I;
+      #cmp{src1=L,src2=R} -> I#cmp{src1=T(L),src2=O(R)};
+      #comment{} -> I;
+      #label{} -> I;
+      #load{dst=D,base=B} -> I#load{dst=T(D),base=T(B)};
+      #loadx{dst=D,base1=L,base2=R} -> I#loadx{dst=T(D),base1=T(L),base2=T(R)};
+      #mfspr{dst=D} -> I#mfspr{dst=T(D)};
+      #mtcr{src=S} -> I#mtcr{src=T(S)};
+      #mtspr{src=S} -> I#mtspr{src=T(S)};
+      #pseudo_bc{} -> I;
+      #pseudo_call{func=F} when not is_record(F, ppc_temp) -> I;
+      #pseudo_call_prepare{} -> I;
+      #pseudo_li{dst=D} -> I#pseudo_li{dst=T(D)};
+      #pseudo_move{dst=D,src=S} -> I#pseudo_move{dst=T(D),src=T(S)};
+      #pseudo_tailcall{func=F,stkargs=Stk} when not is_record(F, ppc_temp) ->
+	  I#pseudo_tailcall{stkargs=lists:map(A,Stk)};
+      #pseudo_tailcall_prepare{} -> I;
+      #store{src=S,base=B} -> I#store{src=T(S),base=T(B)};
+      #storex{src=S,base1=L,base2=R} ->
+	  I#storex{src=T(S),base1=T(L),base2=T(R)};
+      #unary{dst=D,src=S} -> I#unary{dst=T(D),src=T(S)};
+      #lfd{dst=D,base=B} -> I#lfd{dst=T(D),base=T(B)};
+      #lfdx{dst=D,base1=L,base2=R} -> I#lfdx{dst=T(D),base1=T(L),base2=T(R)};
+      #stfd{src=S,base=B} -> I#stfd{src=T(S),base=T(B)};
+      #stfdx{src=S,base1=L,base2=R} -> I#stfdx{src=T(S),base1=T(L),base2=T(R)};
+      #fp_binary{dst=D,src1=L,src2=R} ->
+	  I#fp_binary{dst=T(D),src1=T(L),src2=T(R)};
+      #fp_unary{dst=D,src=S} -> I#fp_unary{dst=T(D),src=T(S)};
+      #pseudo_fmove{dst=D,src=S} -> I#pseudo_fmove{dst=T(D),src=T(S)}
+  end.
+
+-spec oper_temps(subst_fun(), oper()) -> oper().
+oper_temps(SubstTemp,  T=#ppc_temp{}) -> SubstTemp(T);
+oper_temps(_SubstTemp, I=#ppc_simm16{}) -> I;
+oper_temps(_SubstTemp, I=#ppc_uimm16{}) -> I.
+
+-spec arg_temps(subst_fun(), arg()) -> arg().
+arg_temps(_SubstTemp, Imm) when is_integer(Imm) -> Imm;
+arg_temps(SubstTemp,  T=#ppc_temp{}) -> SubstTemp(T).
diff --git a/lib/hipe/regalloc/hipe_ppc_specific.erl b/lib/hipe/regalloc/hipe_ppc_specific.erl
index 3811b972ba..d046567e79 100644
--- a/lib/hipe/regalloc/hipe_ppc_specific.erl
+++ b/lib/hipe/regalloc/hipe_ppc_specific.erl
@@ -53,6 +53,12 @@
 %% callbacks for hipe_regalloc_loop
 -export([check_and_rewrite/2]).
 
+%% callbacks for hipe_regalloc_prepass
+-export([new_reg_nr/0,
+	 update_reg_nr/2,
+	 update_bb/3,
+	 subst_temps/2]).
+
 check_and_rewrite(CFG, Coloring) ->
   hipe_ppc_ra_postconditions:check_and_rewrite(CFG, Coloring, 'normal').
 
@@ -113,6 +119,9 @@ number_of_temporaries(_CFG) ->
 bb(CFG,L) ->
   hipe_ppc_cfg:bb(CFG,L).
 
+update_bb(CFG,L,BB) ->
+  hipe_ppc_cfg:bb_add(CFG,L,BB).
+
 %% PowerPC stuff
 
 def_use(Instruction) ->
@@ -145,6 +154,23 @@ is_move(Instruction) ->
 reg_nr(Reg) ->
   hipe_ppc:temp_reg(Reg).
 
+new_reg_nr() ->
+  hipe_gensym:get_next_var(ppc).
+
+update_reg_nr(Nr, Temp) ->
+  hipe_ppc:mk_temp(Nr, hipe_ppc:temp_type(Temp)).
+
+subst_temps(SubstFun, Instr) ->
+  hipe_ppc_subst:insn_temps(
+    fun(Op) ->
+	case hipe_ppc:temp_is_allocatable(Op)
+	  andalso hipe_ppc:temp_type(Op) =/= 'double'
+	of
+	  true -> SubstFun(Op);
+	  false -> Op
+	end
+    end, Instr).
+
 %%% Linear Scan stuff
 
 new_spill_index(SpillIndex) when is_integer(SpillIndex) ->
diff --git a/lib/hipe/regalloc/hipe_ppc_specific_fp.erl b/lib/hipe/regalloc/hipe_ppc_specific_fp.erl
index 7805d347d6..5ec625daaf 100644
--- a/lib/hipe/regalloc/hipe_ppc_specific_fp.erl
+++ b/lib/hipe/regalloc/hipe_ppc_specific_fp.erl
@@ -53,6 +53,12 @@
 %% callbacks for hipe_regalloc_loop
 -export([check_and_rewrite/2]).
 
+%% callbacks for hipe_regalloc_prepass
+-export([new_reg_nr/0,
+	 update_reg_nr/2,
+	 update_bb/3,
+	 subst_temps/2]).
+
 check_and_rewrite(CFG, Coloring) ->
   hipe_ppc_ra_postconditions_fp:check_and_rewrite(CFG, Coloring).
 
@@ -106,6 +112,9 @@ number_of_temporaries(_CFG) ->
 bb(CFG, L) ->
   hipe_ppc_cfg:bb(CFG, L).
 
+update_bb(CFG,L,BB) ->
+  hipe_ppc_cfg:bb_add(CFG,L,BB).
+
 %% PowerPC stuff
 
 def_use(I) ->
@@ -126,6 +135,23 @@ is_move(I) ->
 reg_nr(Reg) ->
   hipe_ppc:temp_reg(Reg).
 
+new_reg_nr() ->
+  hipe_gensym:get_next_var(ppc).
+
+update_reg_nr(Nr, _Temp) ->
+  hipe_ppc:mk_temp(Nr, 'double').
+
+subst_temps(SubstFun, Instr) ->
+  hipe_ppc_subst:insn_temps(
+    fun(Op) ->
+	case hipe_ppc:temp_is_allocatable(Op)
+	  andalso hipe_ppc:temp_type(Op) =:= 'double'
+	of
+	  true -> SubstFun(Op);
+	  false -> Op
+	end
+    end, Instr).
+
 -ifdef(notdef).
 new_spill_index(SpillIndex) ->
   SpillIndex+1.