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| author | Magnus Lång <[email protected]> | 2016-04-12 18:41:52 +0200 |
|---|---|---|
| committer | Magnus Lång <[email protected]> | 2016-08-30 17:18:00 +0200 |
| commit | 5ffdaa02d53c26fbc41d4bd16575ef9a6ee3c1d7 (patch) | |
| tree | c58ed0f4e64a6d6c1fab45f7029506a21db85a44 /HOWTO/BENCHMARKS.md | |
| parent | 7dd26f1dbbb85af96c80a9a2f272150ba52b0a56 (diff) | |
| download | otp-5ffdaa02d53c26fbc41d4bd16575ef9a6ee3c1d7.tar.gz otp-5ffdaa02d53c26fbc41d4bd16575ef9a6ee3c1d7.tar.bz2 otp-5ffdaa02d53c26fbc41d4bd16575ef9a6ee3c1d7.zip | |
hipe_arm: Be resilient to crappy RTL
The ARM backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
One of the problems were caused by shift-by-immediate-zero, which wraps
to immediate-32 with some shiftops. TODO: Someplace should be modified
to crash when these are generated so debuging further instances of this
gets easier in the future.
Diffstat (limited to 'HOWTO/BENCHMARKS.md')
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