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authorRickard Green <[email protected]>2014-02-24 14:14:24 +0100
committerRickard Green <[email protected]>2014-02-24 14:14:24 +0100
commitce614726e9fb19b462ed41a2f020b68ef98cd532 (patch)
treec61534690567d2ad32671e85d46aedbc02041718 /erts/emulator/beam/erl_alloc.h
parent15c4e79462cd890c2782fc14c9ac9b8cf99ee46f (diff)
parentb2017b91a5572f7bc2caf15082b4b105f3a3e21d (diff)
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Merge branch 'rickard/assumed-cacheline-size/OTP-11742'
* rickard/assumed-cacheline-size/OTP-11742: Introduce configure option --with-assumed-cache-line-size=SIZE
Diffstat (limited to 'erts/emulator/beam/erl_alloc.h')
-rw-r--r--erts/emulator/beam/erl_alloc.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/erts/emulator/beam/erl_alloc.h b/erts/emulator/beam/erl_alloc.h
index f83f6b39cf..942eaa47d0 100644
--- a/erts/emulator/beam/erl_alloc.h
+++ b/erts/emulator/beam/erl_alloc.h
@@ -209,8 +209,8 @@ int erts_is_allctr_wrapper_prelocked(void);
void *erts_alloc_permanent_cache_aligned(ErtsAlcType_t type, Uint size);
#ifndef ERTS_CACHE_LINE_SIZE
-/* Assume a cache line size of 64 bytes */
-# define ERTS_CACHE_LINE_SIZE ((UWord) 64)
+/* Assumed cache line size */
+# define ERTS_CACHE_LINE_SIZE ((UWord) ASSUMED_CACHE_LINE_SIZE)
# define ERTS_CACHE_LINE_MASK (ERTS_CACHE_LINE_SIZE - 1)
#endif