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| author | Sverker Eriksson <[email protected]> | 2011-11-09 21:07:55 +0100 |
|---|---|---|
| committer | Sverker Eriksson <[email protected]> | 2011-11-09 21:07:55 +0100 |
| commit | a4b82870313b04a51cc2d71f6d5a420b386cec68 (patch) | |
| tree | 2368147f9b260058dd49ea5e587b603548f1e2d0 /erts/emulator/hipe/hipe_ppc_asm.m4 | |
| parent | d82c450402b4fe030befc28cc77e3bc2c07001c1 (diff) | |
| parent | 79e5d78244143e0c891f87e9971c9598c4cdea4c (diff) | |
| download | otp-a4b82870313b04a51cc2d71f6d5a420b386cec68.tar.gz otp-a4b82870313b04a51cc2d71f6d5a420b386cec68.tar.bz2 otp-a4b82870313b04a51cc2d71f6d5a420b386cec68.zip | |
Merge branch 'sverk/bif-args/OTP-9662'
* sverk/bif-args/OTP-9662:
erts,hipe: Limited support for hipe cross compilation
erts-hipe: Change THE_NON_VALUE for HiPE enabled debug emulator
erts-hipe: Enable debug compiled hipe-VM with lock checker
erts-hipe: Rename fail_bif_interface_0 to standard_bif_interface_0
erts-hipe: Deliberate leak of native fun entries
erts-hipe: Fix new trap conventions for x86, amd64 and ppc
Store the trap address in p->i
Store the trap arguments in the X register array
erts-hipe: Make some primops use new BIF calling convention
erts-hipe: Adapt generated BIF wrappers for new calling convention
erts-hipe: Remove obscuring macros in generated assembler code
erts-hipe: Make hipe enabled emulator compile with new BIF calls
Simplify the instructions for calling BIFs
Change the calling convention for BIFs
Use the proper macros in all BIFs
Conflicts:
erts/emulator/beam/bif.h
erts/emulator/beam/erl_bif_info.c
Diffstat (limited to 'erts/emulator/hipe/hipe_ppc_asm.m4')
| -rw-r--r-- | erts/emulator/hipe/hipe_ppc_asm.m4 | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/erts/emulator/hipe/hipe_ppc_asm.m4 b/erts/emulator/hipe/hipe_ppc_asm.m4 index 0eb5c441e6..343402f9f0 100644 --- a/erts/emulator/hipe/hipe_ppc_asm.m4 +++ b/erts/emulator/hipe/hipe_ppc_asm.m4 @@ -31,12 +31,23 @@ define(LOAD,ld)dnl define(STORE,std)dnl define(CMPI,cmpdi)dnl define(WSIZE,8)dnl +`#define STORE_IA(ADDR, DST, TMP) \ + addis TMP, 0, ADDR@highest SEMI\ + ori TMP, TMP, ADDR@higher SEMI\ + rldicr TMP, TMP, 32, 31 SEMI\ + oris TMP, TMP, ADDR@h SEMI\ + ori TMP, TMP, ADDR@l SEMI\ + std TMP, DST' ',` /* 32-bit PowerPC */ define(LOAD,lwz)dnl define(STORE,stw)dnl define(CMPI,cmpwi)dnl define(WSIZE,4)dnl +`#define STORE_IA(ADDR, DST, TMP) \ + lis TMP, ADDR@ha SEMI\ + addi TMP, TMP, ADDR@l SEMI\ + stw TMP, DST' ')dnl `#define LOAD 'LOAD `#define STORE 'STORE |