Merge branch 'egil/ansi-pedantic' into maint

2 files changed, 10 insertions, 10 deletions

diff --git a/erts/emulator/sys/common/erl_mseg.c b/erts/emulator/sys/common/erl_mseg.c
index bd8ba82a5f..f5a29fcb95 100644
--- a/erts/emulator/sys/common/erl_mseg.c
+++ b/erts/emulator/sys/common/erl_mseg.c
@@ -350,7 +350,7 @@ schedule_cache_check(ErtsMsegAllctr_t *ma) {
 static ERTS_INLINE void *
 mmap_align(ErtsMsegAllctr_t *ma, void *addr, size_t length, int prot, int flags, int fd, off_t offset) {
 
-    void *p, *q;
+    char *p, *q;
     UWord d;
 
     p = mmap(addr, length, prot, flags, fd, offset);
@@ -366,14 +366,14 @@ mmap_align(ErtsMsegAllctr_t *ma, void *addr, size_t length, int prot, int flags,
     if ((p = mmap(addr, length + MSEG_ALIGNED_SIZE, prot, flags, fd, offset)) == MAP_FAILED)
 	return MAP_FAILED;
 
-    q = (void *)ALIGNED_CEILING(p);
-    d = q - p;
+    q = (void *)ALIGNED_CEILING((char *)p);
+    d = (UWord)(q - p);
 
     if (d > 0)
 	munmap(p, d);
 
     if (MSEG_ALIGNED_SIZE - d > 0)
-	munmap((void *) (q + length), MSEG_ALIGNED_SIZE - d);
+	munmap((void *)(q + length), MSEG_ALIGNED_SIZE - d);
 
     return q;
 }
@@ -708,7 +708,7 @@ static ERTS_INLINE void *cache_get_segment(MemKind *mk, Uint *size_p, Uint flags
 
 	    /* Use current cache placement for remaining segment space */
 
-	    best->seg  = seg + size;
+	    best->seg  = ((char *)seg) + size;
 	    best->size = csize - size;
 
 	    ASSERT((size % GET_PAGE_SIZE) == 0);
diff --git a/erts/emulator/sys/unix/sys_float.c b/erts/emulator/sys/unix/sys_float.c
index f2f4de869d..787f8d6728 100644
--- a/erts/emulator/sys/unix/sys_float.c
+++ b/erts/emulator/sys/unix/sys_float.c
@@ -152,7 +152,7 @@ static int mask_sse2(void)
 
 #if defined(__x86_64__)
 
-static inline int cpu_has_sse2(void) { return 1; }
+static ERTS_INLINE int cpu_has_sse2(void) { return 1; }
 
 #else /* !__x86_64__ */
 
@@ -179,7 +179,7 @@ static unsigned int xor_eflags(unsigned int mask)
     return eax;
 }
 
-static __inline__ unsigned int cpuid_eax(unsigned int op)
+static ERTS_INLINE unsigned int cpuid_eax(unsigned int op)
 {
     unsigned int eax, save_ebx;
 
@@ -195,7 +195,7 @@ static __inline__ unsigned int cpuid_eax(unsigned int op)
     return eax;
 }
 
-static __inline__ unsigned int cpuid_edx(unsigned int op)
+static ERTS_INLINE unsigned int cpuid_edx(unsigned int op)
 {
     unsigned int eax, edx, save_ebx;
  
@@ -215,7 +215,7 @@ static __inline__ unsigned int cpuid_edx(unsigned int op)
  * register on the Intel486 processor to generate alignment
  * faults. This bit cannot be set on the Intel386 processor.
  */
-static __inline__ int is_386(void)
+static ERTS_INLINE int is_386(void)
 {
     return ((xor_eflags(1<<18) >> 18) & 1) == 0;
 }
@@ -223,7 +223,7 @@ static __inline__ int is_386(void)
 /* Newer x86 processors have a CPUID instruction, as indicated by
  * the ID bit (#21) in EFLAGS being modifiable.
  */
-static __inline__ int has_CPUID(void)
+static ERTS_INLINE int has_CPUID(void)
 {
     return (xor_eflags(1<<21) >> 21) & 1;
 }