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authorRickard Green <[email protected]>2011-05-10 11:45:30 +0200
committerRickard Green <[email protected]>2011-05-11 12:11:45 +0200
commit5bcdb3ac4ea27ca47e18628aa147e7544043fa84 (patch)
treefab46e0a588d6e7cab7ef4b42a9280ccd7da3b64 /erts/include/internal/tile/atomic.h
parent2ef48dca9328e0b928117f21bc9ee6dbc5a614cc (diff)
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Homogenize memory barriers on atomics
Atomic operations with specified barriers have specified barrier semantics. Set and read operations have undefined barrier semantics. All other atomic operations implied full memory barriers, except when using the libatomic_ops library and the tilera atomics api. Some code in the runtime system assumed that all operations used (except for set, read and specified) implied full memory barriers. The use of the libatomic_ops library and the tilera atomics api have therefore been modified to behave as the other implementations. Some atomic operations with specified barrier semantics on sparc32 have also been been relaxed in this commit.
Diffstat (limited to 'erts/include/internal/tile/atomic.h')
-rw-r--r--erts/include/internal/tile/atomic.h33
1 files changed, 24 insertions, 9 deletions
diff --git a/erts/include/internal/tile/atomic.h b/erts/include/internal/tile/atomic.h
index 48e4c0c6c8..0c7b597a6b 100644
--- a/erts/include/internal/tile/atomic.h
+++ b/erts/include/internal/tile/atomic.h
@@ -65,25 +65,35 @@ ethr_native_atomic32_read(ethr_native_atomic32_t *var)
static ETHR_INLINE void
ethr_native_atomic32_add(ethr_native_atomic32_t *var, ethr_sint32_t incr)
{
+ ETHR_MEMORY_BARRIER;
atomic_add(&var->counter, incr);
+ ETHR_MEMORY_BARRIER;
}
static ETHR_INLINE void
ethr_native_atomic32_inc(ethr_native_atomic32_t *var)
{
+ ETHR_MEMORY_BARRIER;
atomic_increment(&var->counter);
+ ETHR_MEMORY_BARRIER;
}
static ETHR_INLINE void
ethr_native_atomic32_dec(ethr_native_atomic32_t *var)
{
+ ETHR_MEMORY_BARRIER;
atomic_decrement(&var->counter);
+ ETHR_MEMORY_BARRIER;
}
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_add_return(ethr_native_atomic32_t *var, ethr_sint32_t incr)
{
- return atomic_exchange_and_add(&var->counter, incr) + incr;
+ ethr_sint32_t res;
+ ETHR_MEMORY_BARRIER;
+ res = atomic_exchange_and_add(&var->counter, incr) + incr;
+ ETHR_MEMORY_BARRIER;
+ return res;
}
static ETHR_INLINE ethr_sint32_t
@@ -101,18 +111,27 @@ ethr_native_atomic32_dec_return(ethr_native_atomic32_t *var)
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_and_retold(ethr_native_atomic32_t *var, ethr_sint32_t mask)
{
- return atomic_and_val(&var->counter, mask);
+ ethr_sint32_t res;
+ ETHR_MEMORY_BARRIER;
+ res = atomic_and_val(&var->counter, mask);
+ ETHR_MEMORY_BARRIER;
+ return res;
}
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_or_retold(ethr_native_atomic32_t *var, ethr_sint32_t mask)
{
- return atomic_or_val(&var->counter, mask);
+ ethr_sint32_t res;
+ ETHR_MEMORY_BARRIER;
+ res = atomic_or_val(&var->counter, mask);
+ ETHR_MEMORY_BARRIER;
+ return res;
}
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_xchg(ethr_native_atomic32_t *var, ethr_sint32_t val)
{
+ ETHR_MEMORY_BARRIER;
return atomic_exchange_acq(&var->counter, val);
}
@@ -121,6 +140,7 @@ ethr_native_atomic32_cmpxchg(ethr_native_atomic32_t *var,
ethr_sint32_t new,
ethr_sint32_t expected)
{
+ ETHR_MEMORY_BARRIER;
return atomic_compare_and_exchange_val_acq(&var->counter, new, expected);
}
@@ -139,9 +159,7 @@ ethr_native_atomic32_read_acqb(ethr_native_atomic32_t *var)
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_inc_return_acqb(ethr_native_atomic32_t *var)
{
- ethr_sint32_t res = ethr_native_atomic32_inc_return(var);
- ETHR_MEMORY_BARRIER;
- return res;
+ return ethr_native_atomic32_inc_return(var);
}
static ETHR_INLINE void
@@ -154,14 +172,12 @@ ethr_native_atomic32_set_relb(ethr_native_atomic32_t *var, ethr_sint32_t val)
static ETHR_INLINE void
ethr_native_atomic32_dec_relb(ethr_native_atomic32_t *var)
{
- ETHR_MEMORY_BARRIER;
ethr_native_atomic32_dec(var);
}
static ETHR_INLINE ethr_sint32_t
ethr_native_atomic32_dec_return_relb(ethr_native_atomic32_t *var)
{
- ETHR_MEMORY_BARRIER;
return ethr_native_atomic32_dec_return(var);
}
@@ -178,7 +194,6 @@ ethr_native_atomic32_cmpxchg_relb(ethr_native_atomic32_t *var,
ethr_sint32_t new,
ethr_sint32_t exp)
{
- ETHR_MEMORY_BARRIER;
return ethr_native_atomic32_cmpxchg(var, new, exp);
}