Merge branch 'maint'

* maint:
  Improve cmpxchg8b/cmpxchg16b inline asm
  Improve cmpxchg8b inline asm configure test

2 files changed, 52 insertions, 25 deletions

diff --git a/erts/include/internal/ethread_header_config.h.in b/erts/include/internal/ethread_header_config.h.in
index 9cabd0591a..f4b08cfced 100644
--- a/erts/include/internal/ethread_header_config.h.in
+++ b/erts/include/internal/ethread_header_config.h.in
@@ -166,6 +166,10 @@
 /* Define if you use a gcc that supports the double word cmpxchg instruction */
 #undef ETHR_GCC_HAVE_DW_CMPXCHG_ASM_SUPPORT
 
+/* Define if gcc wont let you clobber ebx with cmpxchg8b and position
+   independent code */
+#undef ETHR_CMPXCHG8B_PIC_NO_CLOBBER_EBX
+
 /* Define if you get a register shortage with cmpxchg8b and position independent code */
 #undef ETHR_CMPXCHG8B_REGISTER_SHORTAGE
 
diff --git a/erts/include/internal/i386/ethr_dw_atomic.h b/erts/include/internal/i386/ethr_dw_atomic.h
index e8c4119ef0..5444a6345c 100644
--- a/erts/include/internal/i386/ethr_dw_atomic.h
+++ b/erts/include/internal/i386/ethr_dw_atomic.h
@@ -115,13 +115,19 @@ ethr_native_dw_atomic_addr(ethr_native_dw_atomic_t *var)
     return (ethr_sint_t *) ETHR_DW_NATMC_MEM__(var);
 }
 
-#if ETHR_SIZEOF_PTR == 4 && defined(__PIC__) && __PIC__
+#if defined(ETHR_CMPXCHG8B_PIC_NO_CLOBBER_EBX) && defined(__PIC__) && __PIC__
+#if ETHR_SIZEOF_PTR != 4
+#  error unexpected pic issue
+#endif
 /*
  * When position independent code is used in 32-bit mode, the EBX register
- * is used for storage of global offset table address, and we may not
- * use it as input or output in an asm. We need to save and restore the
- * EBX register explicitly (for some reason gcc doesn't provide this
- * service to us).
+ * is used for storage of global offset table address. When compiling with
+ * an old gcc (< vsn 5) we may not use it as input or output in an inline
+ * asm. We then need to save and restore the EBX register explicitly (for
+ * some reason old gcc compilers didn't provide this service to us).
+ * ETHR_CMPXCHG8B_PIC_NO_CLOBBER_EBX will be defined if we need to
+ * explicitly manage EBX ourselves.
+ *
  */
 #  define ETHR_NO_CLOBBER_EBX__ 1
 #else
@@ -151,36 +157,53 @@ ethr_native_dw_atomic_cmpxchg_mb(ethr_native_dw_atomic_t *var,
 
     ETHR_DW_DBG_ALIGNED__(p);
 
+#if ETHR_NO_CLOBBER_EBX__ && ETHR_CMPXCHG8B_REGISTER_SHORTAGE
+    /*
+     * gcc wont let us use ebx as input and we
+     * get a register shortage
+     */
+
     __asm__ __volatile__(
-#if ETHR_NO_CLOBBER_EBX__
 	"pushl %%ebx\n\t"
-#  if ETHR_CMPXCHG8B_REGISTER_SHORTAGE
 	"movl (%7), %%ebx\n\t"
 	"movl 4(%7), %%ecx\n\t"
-#  else
-	"movl %8, %%ebx\n\t"
-#  endif
-#endif
-	"lock; cmpxchg" ETHR_DW_CMPXCHG_SFX__ " %0\n\t"
+	"lock; cmpxchg8b %0\n\t"
 	"setz %3\n\t"
-#if ETHR_NO_CLOBBER_EBX__
 	"popl %%ebx\n\t"
-#endif
 	: "=m"(*p), "=d"(xchg[1]), "=a"(xchg[0]), "=c"(xchgd)
-	: "m"(*p), "1"(xchg[1]), "2"(xchg[0]),
-#if ETHR_NO_CLOBBER_EBX__
-#  if ETHR_CMPXCHG8B_REGISTER_SHORTAGE
-	  "3"(new)
-#  else
-	  "3"(new[1]),
-	  "r"(new[0])
-#  endif
+	: "m"(*p), "1"(xchg[1]), "2"(xchg[0]), "r"(new)
+	: "cc", "memory");
+
+#elif ETHR_NO_CLOBBER_EBX__
+    /*
+     * gcc wont let us use ebx as input
+     */
+
+    __asm__ __volatile__(
+	"pushl %%ebx\n\t"
+	"movl %8, %%ebx\n\t"
+	"lock; cmpxchg8b %0\n\t"
+	"setz %3\n\t"
+	"popl %%ebx\n\t"
+	: "=m"(*p), "=d"(xchg[1]), "=a"(xchg[0]), "=q"(xchgd)
+	: "m"(*p), "1"(xchg[1]), "2"(xchg[0]), "c"(new[1]), "r"(new[0])
+	: "cc", "memory");
+
 #else
-	  "3"(new[1]),
-	  "b"(new[0])
-#endif
+    /*
+     * gcc lets us place values in the registers where
+     * we want them
+     */
+
+    __asm__ __volatile__(
+	"lock; cmpxchg" ETHR_DW_CMPXCHG_SFX__ " %0\n\t"
+	"setz %3\n\t"
+	: "=m"(*p), "=d"(xchg[1]), "=a"(xchg[0]), "=q"(xchgd)
+	: "m"(*p), "1"(xchg[1]), "2"(xchg[0]), "c"(new[1]), "b"(new[0])
 	: "cc", "memory");
 
+#endif
+
     return (int) xchgd;
 }