Improve ethread atomics

The ethread atomics API now also provide double word size atomics.
Double word size atomics are implemented using native atomic
instructions on x86 (when the cmpxchg8b instruction is available)
and on x86_64 (when the cmpxchg16b instruction is available). On
other hardware where 32-bit atomics or word size atomics are
available, an optimized fallback is used; otherwise, a spinlock,
or a mutex based fallback is used.

The ethread library now performs runtime tests for presence of
hardware features, such as for example SSE2 instructions, instead
of requiring this to be determined at compile time.

There are now functions implementing each atomic operation with the
following implied memory barrier semantics: none, read, write,
acquire, release, and full. Some of the operation-barrier
combinations aren't especially useful. But instead of filtering
useful ones out, and potentially miss a useful one, we implement
them all.

A much smaller set of functionality for native atomics are required
to be implemented than before. More or less only cmpxchg and a
membar macro are required to be implemented for each atomic size.
Other functions will automatically be constructed from these. It is,
of course, often wise to implement more that this if possible from a
performance perspective.

2 files changed, 132 insertions, 1 deletions

diff --git a/erts/lib_src/pthread/ethr_x86_sse2_asm.c b/erts/lib_src/pthread/ethr_x86_sse2_asm.c
new file mode 100644
index 0000000000..6cbe73cf16
--- /dev/null
+++ b/erts/lib_src/pthread/ethr_x86_sse2_asm.c
@@ -0,0 +1,31 @@
+/*
+ * %CopyrightBegin%
+ *
+ * Copyright Ericsson AB 2011. All Rights Reserved.
+ *
+ * The contents of this file are subject to the Erlang Public License,
+ * Version 1.1, (the "License"); you may not use this file except in
+ * compliance with the License. You should have received a copy of the
+ * Erlang Public License along with this software. If not, it can be
+ * retrieved online at http://www.erlang.org/.
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and limitations
+ * under the License.
+ *
+ * %CopyrightEnd%
+ */
+
+/*
+ * Description: sse2 asm:s
+ * Author: Rickard Green
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+/* ETHR_X86_SSE2_ASM_C__ will trigger asm:s to compile to be included */
+#define ETHR_X86_SSE2_ASM_C__
+#include "ethread.h"
diff --git a/erts/lib_src/pthread/ethread.c b/erts/lib_src/pthread/ethread.c
index f047104103..ad29249bac 100644
--- a/erts/lib_src/pthread/ethread.c
+++ b/erts/lib_src/pthread/ethread.c
@@ -1,7 +1,7 @@
 /*
  * %CopyrightBegin%
  *
- * Copyright Ericsson AB 2010. All Rights Reserved.
+ * Copyright Ericsson AB 2010-2011. All Rights Reserved.
  *
  * The contents of this file are subject to the Erlang Public License,
  * Version 1.1, (the "License"); you may not use this file except in
@@ -121,6 +121,98 @@ ethr_ts_event *ethr_get_tse__(void)
     return pthread_getspecific(ethr_ts_event_key__);
 }
 
+#if defined(ETHR_PPC_RUNTIME_CONF__)
+
+static volatile int lwsync_caused_sigill;
+
+static void
+handle_lwsync_sigill(int signum)
+{
+    lwsync_caused_sigill = 1;
+}
+
+static int
+ppc_init__(void)
+{
+    struct sigaction act, oact;
+    lwsync_caused_sigill = 0;
+
+    sigemptyset(&act.sa_mask);
+    act.sa_flags = 0;
+    act.sa_handler = handle_lwsync_sigill;
+    if (sigaction(SIGILL, &act, &oact) != 0)
+	return errno;
+
+    __asm__ __volatile__ ("lwsync\n\t" : : : "memory");
+
+    act.sa_flags = 0;
+    act.sa_handler = SIG_DFL;
+    if (sigaction(SIGILL, &act, &oact) != 0)
+	return errno;
+
+    ethr_runtime__.conf.have_lwsync = (int) !lwsync_caused_sigill;
+    return 0;
+}
+
+#endif
+
+#if defined(ETHR_X86_RUNTIME_CONF__)
+
+void
+ethr_x86_cpuid__(int *eax, int *ebx, int *ecx, int *edx)
+{
+#if ETHR_SIZEOF_PTR == 4
+    int have_cpuid;
+    /*
+     * If it is possible to toggle eflags bit 21,
+     * we have the cpuid instruction.
+     */
+    __asm__ ("pushf\n\t"
+             "popl %%eax\n\t"
+             "movl %%eax, %%ecx\n\t"
+             "xorl $0x200000, %%eax\n\t"
+             "pushl %%eax\n\t"
+             "popf\n\t"
+             "pushf\n\t"
+             "popl %%eax\n\t"
+             "movl $0x0, %0\n\t"
+             "xorl %%ecx, %%eax\n\t"
+             "jz no_cpuid\n\t"
+	     "movl $0x1, %0\n\t"
+             "no_cpuid:\n\t"
+             : "=r"(have_cpuid)
+             :
+             : "%eax", "%ecx", "cc");
+    if (!have_cpuid) {
+	*eax = *ebx = *ecx = *edx = 0;
+	return;
+    }
+#endif
+#if ETHR_SIZEOF_PTR == 4 && defined(__PIC__) && __PIC__
+    /*
+     * When position independet code is used in 32-bit mode, the B register
+     * is used for storage of global offset table address, and we may not
+     * use it as input or output in an asm. We need to save and restore the
+     * B register explicitly (for some reason gcc doesn't provide this
+     * service to us).
+     */
+    __asm__ ("pushl %%ebx\n\t"
+	     "cpuid\n\t"
+	     "movl %%ebx, %1\n\t"
+	     "popl %%ebx\n\t"
+	     : "=a"(*eax), "=r"(*ebx), "=c"(*ecx), "=d"(*edx)
+	     : "0"(*eax)
+	     : "cc");
+#else
+    __asm__ ("cpuid\n\t"
+	     : "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
+	     : "0"(*eax)
+	     : "cc");
+#endif
+}
+
+#endif /* ETHR_X86_RUNTIME_CONF__ */
+
 /*
  * --------------------------------------------------------------------------
  * Exported functions
@@ -137,6 +229,12 @@ ethr_init(ethr_init_data *id)
 
     ethr_not_inited__ = 0;
 
+#if defined(ETHR_PPC_RUNTIME_CONF__)
+    res = ppc_init__();
+    if (res != 0)
+	goto error;
+#endif
+
     res = ethr_init_common__(id);
     if (res != 0)
 	goto error;
@@ -146,6 +244,8 @@ ethr_init(ethr_init_data *id)
 	child_wait_spin_count = 0;
 
     res = pthread_key_create(&ethr_ts_event_key__, ethr_ts_event_destructor__);
+    if (res != 0)
+	goto error;
 
     return 0;
  error: