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authorMagnus Lång <[email protected]>2017-03-16 15:30:00 +0100
committerMagnus Lång <[email protected]>2017-03-16 20:49:42 +0100
commitc52b2cf226cb3f1bb1b16bee28d47785506adff3 (patch)
treef016829f93e26db7fe7e2329ace868f4b2442510 /lib/hipe/arm/hipe_arm.erl
parentd1d26f4bf9da3cc5eab4e918df771d67fe9e6bb5 (diff)
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hipe: Add pseudo_spill_f?move instructions
These pseudo instructions are added to all backends and allow spill slot to spill slot move coalescing in a clean way. They have regular move semantics, but contain an additional scratch register to be used if both source and destination are spilled, and can not be move coalesced. Additionally, a register allocator callback Target:is_spill_move(Instr, Context) is added which allows the spill slot allocators to check for these instructions and try to coalesce the spill slots the two temporaries are allocated to.
Diffstat (limited to 'lib/hipe/arm/hipe_arm.erl')
-rw-r--r--lib/hipe/arm/hipe_arm.erl7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/hipe/arm/hipe_arm.erl b/lib/hipe/arm/hipe_arm.erl
index e34a00f561..3b090b501a 100644
--- a/lib/hipe/arm/hipe_arm.erl
+++ b/lib/hipe/arm/hipe_arm.erl
@@ -79,6 +79,9 @@
pseudo_move_dst/1,
pseudo_move_src/1,
+ mk_pseudo_spill_move/3,
+ is_pseudo_spill_move/1,
+
mk_pseudo_switch/3,
mk_pseudo_tailcall/4,
@@ -250,6 +253,10 @@ is_pseudo_move(I) -> case I of #pseudo_move{} -> true; _ -> false end.
pseudo_move_dst(#pseudo_move{dst=Dst}) -> Dst.
pseudo_move_src(#pseudo_move{src=Src}) -> Src.
+mk_pseudo_spill_move(Dst, Temp, Src) ->
+ #pseudo_spill_move{dst=Dst, temp=Temp, src=Src}.
+is_pseudo_spill_move(I) -> is_record(I, pseudo_spill_move).
+
mk_pseudo_switch(JTab, Index, Labels) ->
#pseudo_switch{jtab=JTab, index=Index, labels=Labels}.