Merge branch 'sverker/hipe-performance-o1/PR-1154/OTP-13862'

* sverker/hipe-performance-o1/PR-1154:
  hipe_sparc: Minimise CFG<->linear conversions
  hipe_ppc: Minimise CFG<->linear conversions
  hipe_arm: Minimise CFG<->linear conversions
  hipe_x86: Use lea instead of move+add
  hipe_arm: Improve peephole optimiser
  hipe_arm: Be resilient to crappy RTL
  hipe_ppc: Be resilient to crappy RTL
  hipe_sparc: Be resilient to crappy RTL
  hipe: Reuse liveness info for spillmin
  hipe_x86: Minimise CFG<->linear conversions
  hipe: Fix o0 and o1
  hipe: Add o0 and o1 to tests
  hipe_rtl_binary:get_word_integer/4: Handle imms
  hipe_x86: Be resilient to crappy RTL
  hipe_x86: LSRA for SSE2

1 files changed, 21 insertions, 11 deletions

diff --git a/lib/hipe/arm/hipe_rtl_to_arm.erl b/lib/hipe/arm/hipe_rtl_to_arm.erl
index 93342aba33..2f9181d517 100644
--- a/lib/hipe/arm/hipe_rtl_to_arm.erl
+++ b/lib/hipe/arm/hipe_rtl_to_arm.erl
@@ -138,7 +138,6 @@ mk_shift(S, Dst, Src1, ShiftOp, Src2) ->
   end.
 
 mk_shift_ii(S, Dst, Src1, ShiftOp, Src2) ->
-  io:format("~w: RTL alu with two immediates\n", [?MODULE]),
   Tmp = new_untagged_temp(),
   mk_li(Tmp, Src1,
 	mk_shift_ri(S, Dst, Tmp, ShiftOp, Src2)).
@@ -179,7 +178,6 @@ mk_arith(S, Dst, Src1, ArithOp, Src2) ->
   end.
 
 mk_arith_ii(S, Dst, Src1, ArithOp, Src2) ->
-  io:format("~w: RTL alu with two immediates\n", [?MODULE]),
   Tmp = new_untagged_temp(),
   mk_li(Tmp, Src1,
 	mk_arith_ri(S, Dst, Tmp, ArithOp, Src2)).
@@ -277,7 +275,6 @@ mk_branch(Src1, Cond, Src2, TrueLab, FalseLab, Pred) ->
   end.
 
 mk_branch_ii(Imm1, Cond, Imm2, TrueLab, FalseLab, Pred) ->
-  io:format("~w: RTL branch with two immediates\n", [?MODULE]),
   Tmp = new_untagged_temp(),
   mk_li(Tmp, Imm1,
 	mk_branch_ri(Tmp, Cond, Imm2,
@@ -472,7 +469,6 @@ mk_load(Dst, Base1, Base2, LoadSize, LoadSign) ->
   end.
 
 mk_load_ii(Dst, Base1, Base2, LdOp) ->
-  io:format("~w: RTL load with two immediates\n", [?MODULE]),
   Tmp = new_untagged_temp(),
   mk_li(Tmp, Base1,
 	mk_load_ri(Dst, Tmp, Base2, LdOp)).
@@ -485,7 +481,6 @@ mk_load_rr(Dst, Base1, Base2, LdOp) ->
   [hipe_arm:mk_load(LdOp, Dst, Am2)].
 
 mk_ldrsb_ii(Dst, Base1, Base2) ->
-  io:format("~w: RTL load signed byte with two immediates\n", [?MODULE]),
   Tmp = new_untagged_temp(),
   mk_li(Tmp, Base1,
 	mk_ldrsb_ri(Dst, Tmp, Base2)).
@@ -543,7 +538,7 @@ conv_return(I, Map, Data) ->
   {I2, Map0, Data}.
 
 conv_store(I, Map, Data) ->
-  {Base, Map0} = conv_dst(hipe_rtl:store_base(I), Map),
+  {Base, Map0} = conv_src(hipe_rtl:store_base(I), Map),
   {Src, Map1} = conv_src(hipe_rtl:store_src(I), Map0),
   {Offset, Map2} = conv_src(hipe_rtl:store_offset(I), Map1),
   StoreSize = hipe_rtl:store_size(I),
@@ -567,13 +562,28 @@ mk_store(Src, Base, Offset, StoreSize) ->
   end.
 
 mk_store2(Src, Base, Offset, StOp) ->
-  case hipe_arm:is_temp(Offset) of
+  case hipe_arm:is_temp(Base) of
     true ->
-      mk_store_rr(Src, Base, Offset, StOp);
-    _ ->
-      mk_store_ri(Src, Base, Offset, StOp)
+      case hipe_arm:is_temp(Offset) of
+	true ->
+	  mk_store_rr(Src, Base, Offset, StOp);
+	_ ->
+	  mk_store_ri(Src, Base, Offset, StOp)
+      end;
+    false ->
+      case hipe_arm:is_temp(Offset) of
+	true ->
+	  mk_store_ri(Src, Offset, Base, StOp);
+	_ ->
+	  mk_store_ii(Src, Base, Offset, StOp)
+      end
   end.
-  
+
+mk_store_ii(Src, Base, Offset, StOp) ->
+  Tmp = new_untagged_temp(),
+  mk_li(Tmp, Base,
+	mk_store_ri(Src, Tmp, Offset, StOp)).
+
 mk_store_ri(Src, Base, Offset, StOp) ->
   hipe_arm:mk_store(StOp, Src, Base, Offset, 'new', []).