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| author | Magnus Lång <[email protected]> | 2017-03-16 15:30:00 +0100 |
|---|---|---|
| committer | Magnus Lång <[email protected]> | 2017-03-16 20:49:42 +0100 |
| commit | c52b2cf226cb3f1bb1b16bee28d47785506adff3 (patch) | |
| tree | f016829f93e26db7fe7e2329ace868f4b2442510 /lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | |
| parent | d1d26f4bf9da3cc5eab4e918df771d67fe9e6bb5 (diff) | |
| download | otp-c52b2cf226cb3f1bb1b16bee28d47785506adff3.tar.gz otp-c52b2cf226cb3f1bb1b16bee28d47785506adff3.tar.bz2 otp-c52b2cf226cb3f1bb1b16bee28d47785506adff3.zip | |
hipe: Add pseudo_spill_f?move instructions
These pseudo instructions are added to all backends and allow spill slot
to spill slot move coalescing in a clean way.
They have regular move semantics, but contain an additional scratch
register to be used if both source and destination are spilled, and can
not be move coalesced.
Additionally, a register allocator callback
Target:is_spill_move(Instr, Context) is added which allows the spill
slot allocators to check for these instructions and try to coalesce the
spill slots the two temporaries are allocated to.
Diffstat (limited to 'lib/hipe/regalloc/hipe_amd64_specific_sse2.erl')
| -rw-r--r-- | lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl index 8914e7cac3..d592ba391c 100644 --- a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl +++ b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl @@ -30,6 +30,7 @@ def_use/2, is_arg/2, %% used by hipe_ls_regalloc is_move/2, + is_spill_move/2, is_fixed/2, %% used by hipe_graph_coloring_regalloc is_global/2, is_precoloured/2, @@ -194,6 +195,9 @@ is_move(Instruction, _) -> andalso hipe_x86:is_temp(Dst) andalso hipe_x86:temp_is_allocatable(Dst); false -> false end. + +is_spill_move(Instruction,_) -> + hipe_x86:is_pseudo_spill_fmove(Instruction). reg_nr(Reg, _) -> hipe_x86:temp_reg(Reg). |