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| author | Magnus Lång <[email protected]> | 2016-03-12 01:22:45 +0100 |
|---|---|---|
| committer | Magnus Lång <[email protected]> | 2016-08-30 17:02:37 +0200 |
| commit | d93a42112b35e4dbfb0f34b413fffb543f15ca3e (patch) | |
| tree | 1de60981f1c99cfc66fa7e911063f1cc4ee58679 /lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | |
| parent | 85234b4069c9b75e3ae5ddf643b981d7428fb81f (diff) | |
| download | otp-d93a42112b35e4dbfb0f34b413fffb543f15ca3e.tar.gz otp-d93a42112b35e4dbfb0f34b413fffb543f15ca3e.tar.bz2 otp-d93a42112b35e4dbfb0f34b413fffb543f15ca3e.zip | |
hipe_x86: LSRA for SSE2
There is little point offering LSRA for x86 if we're still going to call
hipe_graph_coloring_regalloc for the floats. In particular, all
allocators except LSRA allocates an N^2 interference matrix, making them
unusable for really large functions.
Diffstat (limited to 'lib/hipe/regalloc/hipe_amd64_specific_sse2.erl')
| -rw-r--r-- | lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl index 50e5869d45..8766712ecd 100644 --- a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl +++ b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl @@ -42,7 +42,9 @@ reg_nr/1, non_alloc/1, allocatable/0, - physical_name/1, + allocatable/1, + temp0/0, + physical_name/1, all_precoloured/0, new_spill_index/1, %% used by hipe_ls_regalloc var_range/1, @@ -52,7 +54,8 @@ %% callbacks for hipe_regalloc_loop -export([defun_to_cfg/1, - check_and_rewrite/2]). + check_and_rewrite/2, + check_and_rewrite/3]). %%---------------------------------------------------------------------------- @@ -66,6 +69,10 @@ defun_to_cfg(Defun) -> check_and_rewrite(Defun, Coloring) -> hipe_amd64_ra_sse2_postconditions:check_and_rewrite(Defun, Coloring). +check_and_rewrite(Defun, Coloring, Strategy) -> + hipe_amd64_ra_sse2_postconditions:check_and_rewrite( + Defun, Coloring, Strategy). + reverse_postorder(CFG) -> hipe_x86_cfg:reverse_postorder(CFG). @@ -75,8 +82,8 @@ breadthorder(CFG) -> postorder(CFG) -> hipe_x86_cfg:postorder(CFG). -is_global(_Reg) -> - false. +is_global(Reg) -> + hipe_amd64_registers:sse2_temp0() =:= Reg. is_fixed(_Reg) -> false. @@ -109,7 +116,16 @@ liveout(BB_in_out_liveness, Label) -> %% Registers stuff allocatable() -> - hipe_amd64_registers:allocatable_sse2(). + allocatable('normal'). + +allocatable('normal') -> + hipe_amd64_registers:allocatable_sse2(); +allocatable('linearscan') -> + hipe_amd64_registers:allocatable_sse2() -- + [hipe_amd64_registers:sse2_temp0()]. + +temp0() -> + hipe_amd64_registers:sse2_temp0(). all_precoloured() -> allocatable(). |