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| author | Magnus Lång <[email protected]> | 2016-03-17 21:37:26 +0100 |
|---|---|---|
| committer | Magnus Lång <[email protected]> | 2016-08-30 17:17:45 +0200 |
| commit | dc4e9384c6f2f733ab0d12727ab53238bda3fbca (patch) | |
| tree | 55c4d84effc98ae0bffbd9b7bc185d2d0a602ba6 /lib/hipe/regalloc/hipe_coalescing_regalloc.erl | |
| parent | 4b8c17b0901dfa356792c36f01d78de827cb6645 (diff) | |
| download | otp-dc4e9384c6f2f733ab0d12727ab53238bda3fbca.tar.gz otp-dc4e9384c6f2f733ab0d12727ab53238bda3fbca.tar.bz2 otp-dc4e9384c6f2f733ab0d12727ab53238bda3fbca.zip | |
hipe_x86: Minimise CFG<->linear conversions
Most x86 passes were either linearise(pass(to_cfg(Code))) or trivially
rewritable to process a CFG. This saves a great deal of time and memory
churn when compiling large programs.
Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_x86_main.
Diffstat (limited to 'lib/hipe/regalloc/hipe_coalescing_regalloc.erl')
0 files changed, 0 insertions, 0 deletions