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author | Magnus Lång <[email protected]> | 2016-06-16 17:09:13 +0200 |
---|---|---|
committer | Magnus Lång <[email protected]> | 2016-09-02 15:59:17 +0200 |
commit | 86eeae878efbbcfb12245cdab992bb39987f09bf (patch) | |
tree | ba4befb9ea600fabf88cdcd1a8dd924e003d9141 /lib/hipe/regalloc | |
parent | dcfd9d92a4dce86e9a78b6152523a6eb305e8a6d (diff) | |
download | otp-86eeae878efbbcfb12245cdab992bb39987f09bf.tar.gz otp-86eeae878efbbcfb12245cdab992bb39987f09bf.tar.bz2 otp-86eeae878efbbcfb12245cdab992bb39987f09bf.zip |
hipe: Remove defun_to_cfg/1 RA callback
Now that all backends do register allocation on a CFG directly and
define the defun_to_cfg/1 callback as the identity function, it can be
removed.
Diffstat (limited to 'lib/hipe/regalloc')
-rw-r--r-- | lib/hipe/regalloc/hipe_amd64_specific_sse2.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_arm_specific.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_ppc_specific.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_ppc_specific_fp.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_regalloc_loop.erl | 26 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_sparc_specific.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_sparc_specific_fp.erl | 6 | ||||
-rw-r--r-- | lib/hipe/regalloc/hipe_x86_specific.erl | 6 |
8 files changed, 19 insertions, 49 deletions
diff --git a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl index 6ef79ce95d..35d19ef1df 100644 --- a/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl +++ b/lib/hipe/regalloc/hipe_amd64_specific_sse2.erl @@ -54,8 +54,7 @@ reverse_postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2, +-export([check_and_rewrite/2, check_and_rewrite/3]). %%---------------------------------------------------------------------------- @@ -64,9 +63,6 @@ %%---------------------------------------------------------------------------- -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. - check_and_rewrite(CFG, Coloring) -> hipe_amd64_ra_sse2_postconditions:check_and_rewrite(CFG, Coloring). diff --git a/lib/hipe/regalloc/hipe_arm_specific.erl b/lib/hipe/regalloc/hipe_arm_specific.erl index c696668399..614eb22a1f 100644 --- a/lib/hipe/regalloc/hipe_arm_specific.erl +++ b/lib/hipe/regalloc/hipe_arm_specific.erl @@ -51,11 +51,7 @@ -export([breadthorder/1, postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> hipe_arm_ra_postconditions:check_and_rewrite(CFG, Coloring, 'normal'). diff --git a/lib/hipe/regalloc/hipe_ppc_specific.erl b/lib/hipe/regalloc/hipe_ppc_specific.erl index 79ca333865..3811b972ba 100644 --- a/lib/hipe/regalloc/hipe_ppc_specific.erl +++ b/lib/hipe/regalloc/hipe_ppc_specific.erl @@ -51,11 +51,7 @@ -export([breadthorder/1, postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> hipe_ppc_ra_postconditions:check_and_rewrite(CFG, Coloring, 'normal'). diff --git a/lib/hipe/regalloc/hipe_ppc_specific_fp.erl b/lib/hipe/regalloc/hipe_ppc_specific_fp.erl index 4bf1385e0f..7805d347d6 100644 --- a/lib/hipe/regalloc/hipe_ppc_specific_fp.erl +++ b/lib/hipe/regalloc/hipe_ppc_specific_fp.erl @@ -51,11 +51,7 @@ %%-export([breadthorder/1, postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> hipe_ppc_ra_postconditions_fp:check_and_rewrite(CFG, Coloring). diff --git a/lib/hipe/regalloc/hipe_regalloc_loop.erl b/lib/hipe/regalloc/hipe_regalloc_loop.erl index 4a933a890c..34662200e5 100644 --- a/lib/hipe/regalloc/hipe_regalloc_loop.erl +++ b/lib/hipe/regalloc/hipe_regalloc_loop.erl @@ -26,21 +26,20 @@ %%-define(HIPE_INSTRUMENT_COMPILER, true). %% Turn on instrumentation. -include("../main/hipe.hrl"). -ra(Defun, SpillIndex, Options, RegAllocMod, TargetMod) -> - {NewDefun, Coloring, _NewSpillIndex} = - ra_common(Defun, SpillIndex, Options, RegAllocMod, TargetMod), - {NewDefun, Coloring}. +ra(CFG, SpillIndex, Options, RegAllocMod, TargetMod) -> + {NewCFG, Coloring, _NewSpillIndex} = + ra_common(CFG, SpillIndex, Options, RegAllocMod, TargetMod), + {NewCFG, Coloring}. -ra_fp(Defun, Options, RegAllocMod, TargetMod) -> - ra_common(Defun, 0, Options, RegAllocMod, TargetMod). +ra_fp(CFG, Options, RegAllocMod, TargetMod) -> + ra_common(CFG, 0, Options, RegAllocMod, TargetMod). -ra_common(Defun, SpillIndex, Options, RegAllocMod, TargetMod) -> +ra_common(CFG, SpillIndex, Options, RegAllocMod, TargetMod) -> ?inc_counter(ra_calls_counter, 1), - CFG = TargetMod:defun_to_cfg(Defun), SpillLimit = TargetMod:number_of_temporaries(CFG), - alloc(Defun, CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod). + alloc(CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod). -alloc(Defun, CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) -> +alloc(CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) -> ?inc_counter(ra_iteration_counter, 1), {Coloring, _NewSpillIndex, Liveness} = case proplists:get_bool(ra_prespill, Options) of @@ -50,7 +49,7 @@ alloc(Defun, CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) -> false -> RegAllocMod:regalloc(CFG, SpillIndex, SpillLimit, TargetMod, Options) end, - {NewDefun, DidSpill} = TargetMod:check_and_rewrite(Defun, Coloring), + {NewCFG, DidSpill} = TargetMod:check_and_rewrite(CFG, Coloring), case DidSpill of false -> %% No new temps, we are done. ?add_spills(Options, _NewSpillIndex), @@ -66,10 +65,9 @@ alloc(Defun, CFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) -> %% false -> %% ok %% end, - {NewDefun, Coloring2, NewSpillIndex2}; + {NewCFG, Coloring2, NewSpillIndex2}; _ -> - NewCFG = TargetMod:defun_to_cfg(NewDefun), %% Since SpillLimit is used as a low-water-mark %% the list of temps not to spill is uninteresting. - alloc(NewDefun, NewCFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) + alloc(NewCFG, SpillLimit, SpillIndex, Options, RegAllocMod, TargetMod) end. diff --git a/lib/hipe/regalloc/hipe_sparc_specific.erl b/lib/hipe/regalloc/hipe_sparc_specific.erl index 7df1bbe113..8a792a4fab 100644 --- a/lib/hipe/regalloc/hipe_sparc_specific.erl +++ b/lib/hipe/regalloc/hipe_sparc_specific.erl @@ -51,11 +51,7 @@ -export([breadthorder/1, postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> hipe_sparc_ra_postconditions:check_and_rewrite(CFG, Coloring, 'normal'). diff --git a/lib/hipe/regalloc/hipe_sparc_specific_fp.erl b/lib/hipe/regalloc/hipe_sparc_specific_fp.erl index fd80053708..18f4a6b684 100644 --- a/lib/hipe/regalloc/hipe_sparc_specific_fp.erl +++ b/lib/hipe/regalloc/hipe_sparc_specific_fp.erl @@ -51,11 +51,7 @@ %%-export([breadthorder/1, postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> hipe_sparc_ra_postconditions_fp:check_and_rewrite(CFG, Coloring). diff --git a/lib/hipe/regalloc/hipe_x86_specific.erl b/lib/hipe/regalloc/hipe_x86_specific.erl index 2720af92c1..d5acdc0bd5 100644 --- a/lib/hipe/regalloc/hipe_x86_specific.erl +++ b/lib/hipe/regalloc/hipe_x86_specific.erl @@ -66,11 +66,7 @@ reverse_postorder/1]). %% callbacks for hipe_regalloc_loop --export([defun_to_cfg/1, - check_and_rewrite/2]). - -defun_to_cfg(AlreadyACFG) -> - AlreadyACFG. +-export([check_and_rewrite/2]). check_and_rewrite(CFG, Coloring) -> ?HIPE_X86_RA_POSTCONDITIONS:check_and_rewrite(CFG, Coloring, 'normal'). |