hipe: backends: correct #fconv{} translation

RTL can produce an #fconv{} instruction with an immediate operand, but
the backends unconditionally access the operand as a temporary.  This
results in broken representation in the backends and eventually they
crash.

1 files changed, 5 insertions, 5 deletions

diff --git a/lib/hipe/sparc/hipe_rtl_to_sparc.erl b/lib/hipe/sparc/hipe_rtl_to_sparc.erl
index dc001f865e..fd21be3ae7 100644
--- a/lib/hipe/sparc/hipe_rtl_to_sparc.erl
+++ b/lib/hipe/sparc/hipe_rtl_to_sparc.erl
@@ -85,17 +85,17 @@ conv_insn(I, Map, Data) ->
   end.
 
 conv_fconv(I, Map, Data) ->
-  %% Dst := (double)Src, where Dst is FP reg and Src is int reg
-  {Src, Map1} = conv_src(hipe_rtl:fconv_src(I), Map), % exclude imm src
+  %% Dst := (double)Src, where Dst is FP reg and Src is GP reg or imm
+  {Src, Map1} = conv_src(hipe_rtl:fconv_src(I), Map),
   {Dst, Map2} = conv_fpreg(hipe_rtl:fconv_dst(I), Map1),
   I2 = mk_fconv(Src, Dst),
   {I2, Map2, Data}.
 
 mk_fconv(Src, Dst) ->
   CSP = hipe_sparc:mk_temp(14, 'untagged'), % o6
-  Disp = hipe_sparc:mk_simm13(100),
-  [hipe_sparc:mk_store('stw', Src, CSP, Disp),
-   hipe_sparc:mk_pseudo_fload(CSP, Disp, Dst, true),
+  Offset = 100,
+  mk_store('stw', Src, CSP, Offset) ++
+  [hipe_sparc:mk_pseudo_fload(CSP, hipe_sparc:mk_simm13(Offset), Dst, true),
    hipe_sparc:mk_fp_unary('fitod', Dst, Dst)].
 
 conv_fmove(I, Map, Data) ->