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authorHans Bolinder <[email protected]>2012-03-01 11:48:20 +0100
committerHans Bolinder <[email protected]>2012-03-01 11:48:20 +0100
commitfbdf7929b87f3e41b0ff573b8eaae44cdfae16d9 (patch)
tree57c75cd725c132672c0b74d52176e1e82f1fd896 /lib/stdlib
parent3750ac230e0af600417fff900b3d5ef242fb18c7 (diff)
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Remove loops from the graph created by digraph_utils:condensation/1
The function digraph_utils:condensation/1 used to create a digraph containing loops contradicting the documentation which states that the created digraph is free of cycles. Thanks to Kostis Sagonas for finding the bug.
Diffstat (limited to 'lib/stdlib')
-rw-r--r--lib/stdlib/doc/src/digraph_utils.xml4
-rw-r--r--lib/stdlib/src/digraph_utils.erl4
-rw-r--r--lib/stdlib/test/digraph_utils_SUITE.erl5
3 files changed, 6 insertions, 7 deletions
diff --git a/lib/stdlib/doc/src/digraph_utils.xml b/lib/stdlib/doc/src/digraph_utils.xml
index e44632bfd2..ef6e1cb46f 100644
--- a/lib/stdlib/doc/src/digraph_utils.xml
+++ b/lib/stdlib/doc/src/digraph_utils.xml
@@ -4,7 +4,7 @@
<erlref>
<header>
<copyright>
- <year>2000</year><year>2011</year>
+ <year>2000</year><year>2012</year>
<holder>Ericsson AB. All Rights Reserved.</holder>
</copyright>
<legalnotice>
@@ -156,7 +156,7 @@
<p>Creates a digraph where the vertices are
the <seealso marker="#strong_components">strongly connected
components</seealso> of <c><anno>Digraph</anno></c> as returned by
- <c>strong_components/1</c>. If X and Y are strongly
+ <c>strong_components/1</c>. If X and Y are two different strongly
connected components, and there exist vertices x and y in X
and Y respectively such that there is an
edge <seealso marker="#emanate">emanating</seealso> from x
diff --git a/lib/stdlib/src/digraph_utils.erl b/lib/stdlib/src/digraph_utils.erl
index e221be15a1..807b5c12a1 100644
--- a/lib/stdlib/src/digraph_utils.erl
+++ b/lib/stdlib/src/digraph_utils.erl
@@ -1,7 +1,7 @@
%%
%% %CopyrightBegin%
%%
-%% Copyright Ericsson AB 1999-2011. All Rights Reserved.
+%% Copyright Ericsson AB 1999-2012. All Rights Reserved.
%%
%% The contents of this file are subject to the Erlang Public License,
%% Version 1.1, (the "License"); you may not use this file except in
@@ -370,5 +370,5 @@ condense('$end_of_table', _T, _SC, _G, _SCG, _I2C) ->
condense(I, T, SC, G, SCG, I2C) ->
[{_,C}] = ets:lookup(I2C, I),
digraph:add_vertex(SCG, C),
- digraph:add_edge(SCG, SC, C),
+ [digraph:add_edge(SCG, SC, C) || C =/= SC],
condense(ets:next(T, I), T, SC, G, SCG, I2C).
diff --git a/lib/stdlib/test/digraph_utils_SUITE.erl b/lib/stdlib/test/digraph_utils_SUITE.erl
index 12c486c25f..6b554c2fb7 100644
--- a/lib/stdlib/test/digraph_utils_SUITE.erl
+++ b/lib/stdlib/test/digraph_utils_SUITE.erl
@@ -1,7 +1,7 @@
%%
%% %CopyrightBegin%
%%
-%% Copyright Ericsson AB 2000-2011. All Rights Reserved.
+%% Copyright Ericsson AB 2000-2012. All Rights Reserved.
%%
%% The contents of this file are subject to the Erlang Public License,
%% Version 1.1, (the "License"); you may not use this file except in
@@ -211,8 +211,7 @@ condensation(Config) when is_list(Config) ->
{lists:sort(V1), lists:sort(V2)}
end,
?line Es = lists:map(Fun, digraph:edges(CG)),
- ?line [{[b],[c]},{[b],[d]},{[e,f,g],[e,f,g]},{[h],[h]},{[i,j],[i,j]}] =
- lists:sort(Es),
+ ?line [{[b],[c]},{[b],[d]}] = lists:sort(Es),
?line true = digraph:delete(CG),
?line true = digraph:delete(G),
ok.