Merge branch 'sverker/hipe-backend-bugs/PR-1146' into maint

7 files changed, 46 insertions, 17 deletions

diff --git a/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl b/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
index 5451f1fe7d..b1f7bd7572 100644
--- a/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
+++ b/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
@@ -87,22 +87,29 @@ do_fp_unop(I, TempMap) ->
 %%% Fix an fmove op.
 do_fmove(I, TempMap) ->
   #fmove{src=Src,dst=Dst} = I,
-  case is_mem_opnd(Dst, TempMap) and is_mem_opnd(Src, TempMap) of
+  case
+    (is_mem_opnd(Src, TempMap) andalso is_mem_opnd(Dst, TempMap))
+    orelse (is_mem_opnd(Src, TempMap) andalso (not is_float_temp(Dst)))
+    orelse ((not is_float_temp(Src)) andalso is_mem_opnd(Dst, TempMap))
+  of
     true ->
-      Tmp = clone(Src),
+      Tmp = spill_temp(double),
       {[#fmove{src=Src, dst=Tmp},I#fmove{src=Tmp,dst=Dst}],
        true};
     false ->
       {[I], false}
   end.
 
+is_float_temp(#x86_temp{type=Type}) -> Type =:= double;
+is_float_temp(#x86_mem{}) -> false.
+
 %%% Check if an operand denotes a memory cell (mem or pseudo).
 
 is_mem_opnd(Opnd, TempMap) ->
   R =
     case Opnd of
       #x86_mem{} -> true;
-      #x86_temp{} -> 
+      #x86_temp{type=double} ->
 	Reg = hipe_x86:temp_reg(Opnd),
 	case hipe_x86:temp_is_allocatable(Opnd) of
 	  true -> 
@@ -176,6 +183,9 @@ clone(Dst) ->
       #x86_mem{} -> hipe_x86:mem_type(Dst);
       #x86_temp{} -> hipe_x86:temp_type(Dst)
     end,
+  spill_temp(Type).
+
+spill_temp(Type) ->
   hipe_x86:mk_new_temp(Type).
 
 %%% Make a certain reg into a clone of Dst
diff --git a/lib/hipe/arm/hipe_arm_registers.erl b/lib/hipe/arm/hipe_arm_registers.erl
index 24cd929d41..dcf039676b 100644
--- a/lib/hipe/arm/hipe_arm_registers.erl
+++ b/lib/hipe/arm/hipe_arm_registers.erl
@@ -67,6 +67,8 @@
 -define(R15, 15).
 -define(LAST_PRECOLOURED, 15). % must handle both GPR and FPR ranges
 
+-define(LR, ?R14).
+
 -define(ARG0, ?R1).
 -define(ARG1, ?R2).
 -define(ARG2, ?R3).
@@ -114,7 +116,7 @@ stack_pointer() -> ?STACK_POINTER.
 
 proc_pointer() -> ?PROC_POINTER.
 
-lr() -> ?R14.
+lr() -> ?LR.
 
 pc() -> ?R15.
 
@@ -198,7 +200,9 @@ call_clobbered() ->		% does the RA strip the type or not?
   ].
 
 tailcall_clobbered() ->		% tailcall crapola needs one temp
-  [{?TEMP1,tagged},{?TEMP1,untagged}].
+  [{?TEMP1,tagged},{?TEMP1,untagged}
+  ,{?LR,tagged},{?LR,untagged}
+  ].
 
 live_at_return() ->
   [%%{?LR,untagged},
diff --git a/lib/hipe/arm/hipe_rtl_to_arm.erl b/lib/hipe/arm/hipe_rtl_to_arm.erl
index ad5a559995..93342aba33 100644
--- a/lib/hipe/arm/hipe_rtl_to_arm.erl
+++ b/lib/hipe/arm/hipe_rtl_to_arm.erl
@@ -148,10 +148,11 @@ mk_shift_ir(S, Dst, Src1, ShiftOp, Src2) ->
   mk_li(Tmp, Src1,
 	mk_shift_rr(S, Dst, Tmp, ShiftOp, Src2)).
 
-mk_shift_ri(S, Dst, Src1, ShiftOp, Src2) when is_integer(Src2) ->
-  if Src2 >= 0, Src2 < 32 -> ok;
-     true -> io:format("~w: excessive immediate shift ~w\n", [?MODULE,Src2])
-  end,
+mk_shift_ri(S, Dst, Src1, ShiftOp, 0)
+  when ShiftOp =:= lsl; ShiftOp =:= lsr; ShiftOp =:= asr ->
+  [hipe_arm:mk_move(S, Dst, Src1)];
+mk_shift_ri(S, Dst, Src1, ShiftOp, Src2)
+  when is_integer(Src2), Src2 > 0, Src2 < 32 ->
   Am1 = {Src1,ShiftOp,Src2},
   [hipe_arm:mk_move(S, Dst, Am1)].
 
diff --git a/lib/hipe/ppc/hipe_ppc.erl b/lib/hipe/ppc/hipe_ppc.erl
index 0fa96162f6..380e791bc1 100644
--- a/lib/hipe/ppc/hipe_ppc.erl
+++ b/lib/hipe/ppc/hipe_ppc.erl
@@ -167,8 +167,10 @@ temp_is_precoloured(#ppc_temp{reg=Reg,type=Type}) ->
     _ -> hipe_ppc_registers:is_precoloured_gpr(Reg)
   end.
 
-mk_simm16(Value) -> #ppc_simm16{value=Value}.
-mk_uimm16(Value) -> #ppc_uimm16{value=Value}.
+mk_simm16(Value) when Value >= -(1 bsl 15), Value < (1 bsl 15) ->
+  #ppc_simm16{value=Value}.
+mk_uimm16(Value) when Value >= 0, Value < (1 bsl 16) ->
+  #ppc_uimm16{value=Value}.
 
 mk_mfa(M, F, A) -> #ppc_mfa{m=M, f=F, a=A}.
 
@@ -240,7 +242,11 @@ mk_li(Dst, Value, Tail) ->   % Dst can be R0
      Value =< 16#7FFFFFFF ->
       mk_li32(Dst, R0, Value, Tail);
      true ->
-      Highest = (Value bsr 48),              % Value@highest
+      Highest = case (Value bsr 48) of       % Value@highest
+		  TopBitSet when TopBitSet >= (1 bsl 15) ->
+		    TopBitSet - (1 bsl 16);  % encoder needs it to be negative
+		  FitsSimm16 -> FitsSimm16
+		end,
       Higher = (Value bsr 32) band 16#FFFF,  % Value@higher
       High = (Value bsr 16) band 16#FFFF,    % Value@h
       Low = Value band 16#FFFF,              % Value@l
diff --git a/lib/hipe/ppc/hipe_ppc_assemble.erl b/lib/hipe/ppc/hipe_ppc_assemble.erl
index ff9da01b11..d89ff6235c 100644
--- a/lib/hipe/ppc/hipe_ppc_assemble.erl
+++ b/lib/hipe/ppc/hipe_ppc_assemble.erl
@@ -175,7 +175,8 @@ do_slwi_opnds(Dst, Src1, {uimm,N}) when is_integer(N), 0 =< N, N < 32 ->
   {Dst, Src1, {sh,N}, {mb,0}, {me,31-N}}.
 
 do_srwi_opnds(Dst, Src1, {uimm,N}) when is_integer(N), 0 =< N, N < 32 ->
-  {Dst, Src1, {sh,32-N}, {mb,N}, {me,31}}.
+  %% SH should be 0 (not 32) when N is 0
+  {Dst, Src1, {sh,(32-N) band 31}, {mb,N}, {me,31}}.
 
 do_srawi_src2({uimm,N}) when  is_integer(N), 0 =< N, N < 32 -> {sh,N}.
 
@@ -184,7 +185,8 @@ do_sldi_opnds(Dst, Src1, {uimm,N}) when is_integer(N), 0 =< N, N < 64 ->
   {Dst, Src1, {sh6,N}, {me6,63-N}}.
 
 do_srdi_opnds(Dst, Src1, {uimm,N}) when is_integer(N), 0 =< N, N < 64 ->
-  {Dst, Src1, {sh6,64-N}, {mb6,N}}.
+  %% SH should be 0 (not 64) when N is 0
+  {Dst, Src1, {sh6,(64-N) band 63}, {mb6,N}}.
 
 do_sradi_src2({uimm,N}) when is_integer(N), 0 =< N, N < 64 -> {sh6,N}.
 
@@ -246,6 +248,7 @@ do_load(I) ->
     case LdOp of
       'ld' -> do_disp_ds(Disp);
       'ldu' -> do_disp_ds(Disp);
+      'lwa' -> do_disp_ds(Disp);
       _ -> do_disp(Disp)
     end,
   NewBase = do_reg(Base),
diff --git a/lib/hipe/sparc/hipe_sparc_registers.erl b/lib/hipe/sparc/hipe_sparc_registers.erl
index 884215702b..6681a10070 100644
--- a/lib/hipe/sparc/hipe_sparc_registers.erl
+++ b/lib/hipe/sparc/hipe_sparc_registers.erl
@@ -86,6 +86,8 @@
 -define(I7, 31).
 -define(LAST_PRECOLOURED,31).	% must handle both GRP and FPR ranges
 
+-define(RA, ?O7).
+
 -define(ARG0, ?O1).
 -define(ARG1, ?O2).
 -define(ARG2, ?O3).
@@ -174,7 +176,7 @@ stack_pointer() -> ?STACK_POINTER.
 
 proc_pointer() -> ?PROC_POINTER.
 
-return_address() -> ?O7.
+return_address() -> ?RA.
 
 g0() -> ?G0.
 
@@ -283,7 +285,9 @@ call_clobbered() ->		% does the RA strip the type or not?
   ].
 
 tailcall_clobbered() ->		% tailcall crapola needs one temp
-  [{?TEMP1,tagged},{?TEMP1,untagged}].
+  [{?TEMP1,tagged},{?TEMP1,untagged}
+  ,{?RA,tagged},{?RA,untagged}
+  ].
 
 live_at_return() ->
   [{?HEAP_POINTER,untagged},
diff --git a/lib/hipe/x86/hipe_x86_postpass.erl b/lib/hipe/x86/hipe_x86_postpass.erl
index 939baeccec..4515822a34 100644
--- a/lib/hipe/x86/hipe_x86_postpass.erl
+++ b/lib/hipe/x86/hipe_x86_postpass.erl
@@ -95,7 +95,8 @@ peep([I=#move{src=#x86_temp{reg=Src}, dst=#x86_temp{reg=Dst}},
 
 %% ElimBinALMDouble
 %% ----------------
-peep([Move=#move{src=Src, dst=Dst}, Alu=#alu{src=Src, dst=Dst}|Insns], Res, Lst) ->
+peep([Move=#move{src=Src, dst=Dst}, Alu=#alu{src=Src, dst=Dst}|Insns], Res, Lst)
+  when not is_record(Dst, x86_mem) ->
   peep([Alu#alu{src=Dst}|Insns], [Move|Res], [elimBinALMDouble|Lst]);