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These pseudo instructions are added to all backends and allow spill slot
to spill slot move coalescing in a clean way.
They have regular move semantics, but contain an additional scratch
register to be used if both source and destination are spilled, and can
not be move coalesced.
Additionally, a register allocator callback
Target:is_spill_move(Instr, Context) is added which allows the spill
slot allocators to check for these instructions and try to coalesce the
spill slots the two temporaries are allocated to.
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Also, use byte form for immediates up to 255, since there's no sign
extension in byte form.
HiPE seems to never generate negative test immediates currently, but we
should at least not output incorrect encodings.
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This allows us to pass around the context data that
hipe_regalloc_prepass needs cleanly, without using process dictionary or
parameterised modules (like it was previous to this change).
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These will not only be useful for hipe_regalloc_prepass, but also, after
the introduction of a mk_move/2 (or similar) callback, for the purpose
of range splitting.
Since the substitution needed to case over all the instructions, a new
module, hipe_x86_subst, was introduced to the x86 backend.
Due to differences in the 'jtab' field of a #jmp_switch{} between x86
and amd64, it regrettably needed to be duplicated to hipe_amd64_subst.
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This is due to the improvements in hipe_temp_map, removing the need for
duplicated logic in the backends.
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hipe_regalloc_prepass speeds up register allocation by spilling any temp
that is live over a call (which clobbers all register).
In order to detect these, a new function was added to the target
interface; defines_all_alloc/1, that takes an instruction and returns a
boolean.
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Most x86 passes were either linearise(pass(to_cfg(Code))) or trivially
rewritable to process a CFG. This saves a great deal of time and memory
churn when compiling large programs.
Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_x86_main.
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There is little point offering LSRA for x86 if we're still going to call
hipe_graph_coloring_regalloc for the floats. In particular, all
allocators except LSRA allocates an N^2 interference matrix, making them
unusable for really large functions.
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Register allocation could transform something like
fmove u32, d99
to
fmove $rdx, 0x20($rsp)
which is an invalid instruction.
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and correct the name of another, erroneously spelt, option in the process.
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OTP-10106
OTP-10107
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environment after a number of bugs are fixed and some features
are added in the documentation build process.
- The arity calculation is updated.
- The module prefix used in the function names for bif's are
removed in the generated links so the links will look like
http://www.erlang.org/doc/man/erlang.html#append_element-2
instead of
http://www.erlang.org/doc/man/erlang.html#erlang:append_element-2
- Enhanced the menu positioning in the html documentation when a
new page is loaded.
- A number of corrections in the generation of man pages (thanks
to Sergei Golovan)
- Moved some man pages to more apropriate sections, pages in
section 4 moved to 5 and pages in 6 moved to 7.
- The legal notice is taken from the xml book file so OTP's
build process can be used for non OTP applications.
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