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hipe_regalloc_loop considers SpillLimit to be an inclusive lower bound,
the allocators considered it to be an exclusive lower bound. The
allocators are changed to also consider it an inclusive lower bound.
This caused the register allocators to occasionally spill the first
"unspillable" temporary. This caused a failure in a newly added
assertion when hipe-compiling dets_v9 on x86.
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This allows us to pass around the context data that
hipe_regalloc_prepass needs cleanly, without using process dictionary or
parameterised modules (like it was previous to this change).
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This is sound because the liveness data structure only stores liveness
info at basic block boundaries, and the rewrites that happen in
TargetSpecific:check_and_rewrite/2 preserves all existing definitions
and uses, and all new liveness intervals, belonging to newly introduced
temporaries, are always local to a basic block, and thus do not show up
in the liveout or livein sets for the basic block.
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For x86, additionally reuse liveness from float LSRA for the GP LSRA.
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