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Currently HiPE amd64 assumes the runtime system code is loaded into
the low 2G of the address space. However, this is not the case when
PIE is enabled, it is loaded into a random location. So trampolines
are required to call BIFs, and also we have first to load the address
of sse2_fnegate_mask to a regisiter before xorpd in fchs.
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It seems that most 3-address adds of temps can be move coalesced.
Therefore, we limit the behaviour added by 1567585dda8 to only affect
immediate adds.
Also, add conversion of immediate mov+sub to lea.
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branch and alub overlap in their use cases, but the backends rely on
knowing that the result is unused in their lowering of branch. By
extending alub so that the destination is optional, it can fully replace
branch.
This simplifies rtl by reducing code duplication and the number of
instructions.
Also, in the x86 and arm backends, we can now use 'test' and
{'tst','mvn','teq'} to lower some alubs without destinations. This is
particularly good for x86, as sequences such as 'is_boxed' type tests
now get shorter (both from not needing a mov to copy the variable, but
also from the fact that 'testb' encodes shorter than 'andq').
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This is primarily useful for heap allocations, as a two-address 'add'
can't be used to both copy the heap pointer to another register, and add
the tag.
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The x86 backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
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RTL can produce an #fconv{} instruction with an immediate operand, but
the backends unconditionally access the operand as a temporary. This
results in broken representation in the backends and eventually they
crash.
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