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Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_sparc_main.
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Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_ppc_main.
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Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_arm_main.
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This is primarily useful for heap allocations, as a two-address 'add'
can't be used to both copy the heap pointer to another register, and add
the tag.
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The ARM backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
One of the problems were caused by shift-by-immediate-zero, which wraps
to immediate-32 with some shiftops. TODO: Someplace should be modified
to crash when these are generated so debuging further instances of this
gets easier in the future.
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The PowerPC backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
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The SPARC backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
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For x86, additionally reuse liveness from float LSRA for the GP LSRA.
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Most x86 passes were either linearise(pass(to_cfg(Code))) or trivially
rewritable to process a CFG. This saves a great deal of time and memory
churn when compiling large programs.
Now, there will only ever be a single Linear->CFG conversion, just after
lowering from RTL, and only ever a single CFG->Linear conversion, just
before the finalise pass. Both of these now happen in hipe_x86_main.
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These options would not do anything, because they would not supress the
'o2' in ?COMPILE_DEFAULTS. Such behaviour is added to expand_options/2.
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Now that x86 is no longer broken with these optimisation levels, we add
them to the test suite to ensure they do not break again.
Bump timeout to 6min since tests are run twice as many times.
The option set of o1 was changed to all optimisations that run fast on
both big and small programs, incurring only a slight compile time
increase compared to the old set, but with a, presumably, significant
improvement to speed of compiled code.
Change o0 register allocator to linear_scan.
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Immediate arguments to get_word_integer/4 would lead to bad but
unreachable RTL being generated. We omit its generation by testing for
immediates and performing the logic at compile time.
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The x86 backend crashes if certain RTL optimisations were omitted,
preventing it from being usable at lower optimisation levels.
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There is little point offering LSRA for x86 if we're still going to call
hipe_graph_coloring_regalloc for the floats. In particular, all
allocators except LSRA allocates an N^2 interference matrix, making them
unusable for really large functions.
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* g-andrade/kernel/fetch_ztream_dictionary/PR-1139/OTP-13842:
Update preloaded modules
Specify min zlib ver on inflateGetDictionary doc
Skip inflateGetDictionary test case if unsupported
zlib: Only link inflateGetDictionary if available
zlib: Add test case for inflateGetDictionary
zlib: support extraction of inflation dictionary
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* peppe/debugger_crash/ERL-191/OTP-13756:
Make sure exit in non-interpreted code doesn't crash the debugger
OTP-13756
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* raimo/gen_statem-callback_mode/OTP-13752:
Include trap_exit in server skeletons
Improve sys debug
Handle exceptions in init/1 and callback_mode/0
Clarify error values
Doc fixes
Rewrite SSH for gen_statem M:callback_mode/0
Rewrite SSL for gen_statem M:callback_mode/0
Rewrite Tools for gen_statem M:callback_mode/0
Rewrite gen_statem docs for M:callback_mode/0
Rewrite gen_statem TCs for M:callback_mode/0
Rewrite gen_statem for M:callback_mode/0
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Register allocation could transform something like
fmove u32, d99
to
fmove $rdx, 0x20($rsp)
which is an invalid instruction.
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Since the link register/return address is restored before stack
arguments are stored to the frame, we must not use it to store a stack
argument. We do that by adding it to the registers clobbered by
pseudo_tailcall_prepare.
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The problem was caused by shift-by-immediate-zero, which wraps to
immediate-32 with some shiftops. TODO: Someplace should be modified to
crash when these are generated so debugging further instances of this
gets easier in the future.
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maint
* gomoripeti/syntax_tools/merl-transform/PR-1123/OTP-13755:
Fix infinite loop in merl_transform
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* bjorn/compiler/binary-literal-matching:
Reinstate optimization of binary literal matching
Strengthen test case added in 8b83bc0b
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* ingela/ssl/ssl_npn_hello_SUITE_precondition:
ssl: Check precondition for ssl_npn_hello_SUITE
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corrected some typo
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105c5b0071 was reverted in dd1162846e because clauses that were
supposed to match would not match. (See 8b83bc0b.)
Reintroduce the optimization, but make sure that we only shortcut
bs_context_to_binary instructions and not bs_start_match2 instructions.
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Don't only test the case that failed; test it exhaustively.
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* maint:
wx: Add missing specs
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* dgud/wx/broken-links:
wx: Add missing specs
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* maint:
Request a larger stacksize for wx thread
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* dgud/wx/increase_wx_stacksize:
Request a larger stacksize for wx thread
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