1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
|
/*
* %CopyrightBegin%
*
* Copyright Ericsson AB 2010. All Rights Reserved.
*
* The contents of this file are subject to the Erlang Public License,
* Version 1.1, (the "License"); you may not use this file except in
* compliance with the License. You should have received a copy of the
* Erlang Public License along with this software. If not, it can be
* retrieved online at http://www.erlang.org/.
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and limitations
* under the License.
*
* %CopyrightEnd%
*/
/*
* Description: Native atomics ethread support when using VC++
* Author: Rickard Green
*/
#ifndef ETHR_WIN_ATOMIC_H__
#define ETHR_WIN_ATOMIC_H__
#if defined(_MSC_VER) && _MSC_VER >= 1400
#define ETHR_HAVE_NATIVE_ATOMICS 1
#if defined(_M_IX86) || defined(_M_AMD64) || defined(_M_IA64)
# define ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__ 1
#else
# define ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__ 0
#endif
#if defined(_M_AMD64) || (defined(_M_IX86) \
&& !defined(ETHR_PRE_PENTIUM4_COMPAT))
# define ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__ 1
#else
# define ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__ 0
#endif
/*
* No configure test checking for interlocked acquire/release
* versions have been written, yet. It should define
* ETHR_HAVE_INTERLOCKED_ACQUIRE_RELEASE_BARRIERS if, and
* only if, all used interlocked operations with barriers
* exists.
*
* Note, that these are pure optimizations for the itanium
* processor.
*/
#include <intrin.h>
#undef ETHR_COMPILER_BARRIER
#define ETHR_COMPILER_BARRIER _ReadWriteBarrier()
#pragma intrinsic(_ReadWriteBarrier)
#pragma intrinsic(_InterlockedCompareExchange)
#if defined(_M_AMD64) || (defined(_M_IX86) \
&& !defined(ETHR_PRE_PENTIUM4_COMPAT))
#include <emmintrin.h>
#include <mmintrin.h>
#pragma intrinsic(_mm_mfence)
#define ETHR_MEMORY_BARRIER _mm_mfence()
#pragma intrinsic(_mm_sfence)
#define ETHR_WRITE_MEMORY_BARRIER _mm_sfence()
#pragma intrinsic(_mm_lfence)
#define ETHR_READ_MEMORY_BARRIER _mm_lfence()
#define ETHR_READ_DEPEND_MEMORY_BARRIER ETHR_COMPILER_BARRIER
#else
#define ETHR_MEMORY_BARRIER \
do { \
volatile long x___ = 0; \
_InterlockedCompareExchange(&x___, (long) 1, (long) 0); \
} while (0)
#endif
#if ETHR_SIZEOF_PTR == 4
#pragma intrinsic(_InterlockedDecrement)
#pragma intrinsic(_InterlockedIncrement)
#pragma intrinsic(_InterlockedExchangeAdd)
#pragma intrinsic(_InterlockedExchange)
#pragma intrinsic(_InterlockedAnd)
#pragma intrinsic(_InterlockedOr)
#ifdef ETHR_HAVE_INTERLOCKED_ACQUIRE_RELEASE_BARRIERS
#pragma intrinsic(_InterlockedExchangeAdd_acq)
#pragma intrinsic(_InterlockedIncrement_acq)
#pragma intrinsic(_InterlockedDecrement_rel)
#pragma intrinsic(_InterlockedCompareExchange_acq)
#pragma intrinsic(_InterlockedCompareExchange_rel)
#endif
#define ETHR_ATMC__(X) X
#ifdef ETHR_HAVE_INTERLOCKED_ACQUIRE_RELEASE_BARRIERS
#define ETHR_ATMC_ACQ__(X) X ## _acq
#define ETHR_ATMC_REL__(X) X ## _rel
#else
#define ETHR_ATMC_ACQ__(X) X
#define ETHR_ATMC_REL__(X) X
#endif
#elif ETHR_SIZEOF_PTR == 8
#pragma intrinsic(_InterlockedDecrement64)
#pragma intrinsic(_InterlockedIncrement64)
#pragma intrinsic(_InterlockedExchangeAdd64)
#pragma intrinsic(_InterlockedExchange64)
#pragma intrinsic(_InterlockedAnd64)
#pragma intrinsic(_InterlockedOr64)
#ifdef ETHR_HAVE_INTERLOCKED_ACQUIRE_RELEASE_BARRIERS
#pragma intrinsic(_InterlockedExchangeAdd64_acq)
#pragma intrinsic(_InterlockedIncrement64_acq)
#pragma intrinsic(_InterlockedDecrement64_rel)
#pragma intrinsic(_InterlockedCompareExchange64_acq)
#pragma intrinsic(_InterlockedCompareExchange64_rel)
#endif
#define ETHR_ATMC__(X) X ## 64
#ifdef ETHR_HAVE_INTERLOCKED_ACQUIRE_RELEASE_BARRIERS
#define ETHR_ATMC_ACQ__(X) X ## 64_acq
#define ETHR_ATMC_REL__(X) X ## 64_rel
#else
#define ETHR_ATMC_ACQ__(X) X ## 64
#define ETHR_ATMC_REL__(X) X ## 64
#endif
#else
#error "Unsupported word size"
#endif
#define ETHR_NATMC_FUNC__(X) ethr_native_atomic_ ## X
#define ETHR_ATMC_T__ ethr_native_atomic_t
#define ETHR_AINT_T__ ethr_sint_t
typedef struct {
volatile ETHR_AINT_T__ value;
} ETHR_ATMC_T__;
#if defined(ETHR_TRY_INLINE_FUNCS) || defined(ETHR_ATOMIC_IMPL__)
static ETHR_INLINE void
ETHR_NATMC_FUNC__(init)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ i)
{
#if ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__
var->value = i;
#else
(void) ETHR_ATMC__(_InterlockedExchange)(&var->value, i);
#endif
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(set)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ i)
{
#if ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__
var->value = i;
#else
(void) ETHR_ATMC__(_InterlockedExchange)(&var->value, i);
#endif
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(read)(ETHR_ATMC_T__ *var)
{
#if ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__
return var->value;
#else
return ETHR_ATMC__(_InterlockedExchangeAdd)(&var->value, (ETHR_AINT_T__) 0);
#endif
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(add)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ incr)
{
(void) ETHR_ATMC__(_InterlockedExchangeAdd)(&var->value, incr);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(add_return)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ i)
{
return ETHR_ATMC__(_InterlockedExchangeAdd)(&var->value, i) + i;
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(inc)(ETHR_ATMC_T__ *var)
{
(void) ETHR_ATMC__(_InterlockedIncrement)(&var->value);
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(dec)(ETHR_ATMC_T__ *var)
{
(void) ETHR_ATMC__(_InterlockedDecrement)(&var->value);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(inc_return)(ETHR_ATMC_T__ *var)
{
return ETHR_ATMC__(_InterlockedIncrement)(&var->value);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(dec_return)(ETHR_ATMC_T__ *var)
{
return ETHR_ATMC__(_InterlockedDecrement)(&var->value);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(and_retold)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ mask)
{
return ETHR_ATMC__(_InterlockedAnd)(&var->value, mask);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(or_retold)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ mask)
{
return ETHR_ATMC__(_InterlockedOr)(&var->value, mask);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(cmpxchg)(ETHR_ATMC_T__ *var,
ETHR_AINT_T__ new,
ETHR_AINT_T__ old)
{
return ETHR_ATMC__(_InterlockedCompareExchange)(&var->value, new, old);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(xchg)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ new)
{
return ETHR_ATMC__(_InterlockedExchange)(&var->value, new);
}
/*
* Atomic ops with at least specified barriers.
*/
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(read_acqb)(ETHR_ATMC_T__ *var)
{
#if ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__
ETHR_AINT_T__ val = var->value;
ETHR_COMPILER_BARRIER;
return val;
#else
return ETHR_ATMC_ACQ__(_InterlockedExchangeAdd)(&var->value,
(ETHR_AINT_T__) 0);
#endif
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(inc_return_acqb)(ETHR_ATMC_T__ *var)
{
return ETHR_ATMC_ACQ__(_InterlockedIncrement)(&var->value);
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(set_relb)(ETHR_ATMC_T__ *var, ETHR_AINT_T__ i)
{
#if ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__
ETHR_COMPILER_BARRIER;
var->value = i;
#else
(void) ETHR_ATMC_REL__(_InterlockedExchange)(&var->value, i);
#endif
}
static ETHR_INLINE void
ETHR_NATMC_FUNC__(dec_relb)(ETHR_ATMC_T__ *var)
{
(void) ETHR_ATMC_REL__(_InterlockedDecrement)(&var->value);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(dec_return_relb)(ETHR_ATMC_T__ *var)
{
return ETHR_ATMC_REL__(_InterlockedDecrement)(&var->value);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(cmpxchg_acqb)(ETHR_ATMC_T__ *var,
ETHR_AINT_T__ new,
ETHR_AINT_T__ old)
{
return ETHR_ATMC_ACQ__(_InterlockedCompareExchange)(&var->value, new, old);
}
static ETHR_INLINE ETHR_AINT_T__
ETHR_NATMC_FUNC__(cmpxchg_relb)(ETHR_ATMC_T__ *var,
ETHR_AINT_T__ new,
ETHR_AINT_T__ old)
{
return ETHR_ATMC_REL__(_InterlockedCompareExchange)(&var->value, new, old);
}
#endif
#undef ETHR_NATMC_FUNC__
#undef ETHR_ATMC_T__
#undef ETHR_AINT_T__
#undef ETHR_READ_AND_SET_WITHOUT_INTERLOCKED_OP__
#undef ETHR_READ_ACQB_AND_SET_RELB_COMPILER_BARRIER_ONLY__
#endif
#endif
|
