aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorSverker Eriksson <[email protected]>2019-06-10 19:57:39 +0200
committerSverker Eriksson <[email protected]>2019-06-10 19:57:39 +0200
commita8ba18249d6fd3a913f320bdeeb8b9ea5eef2888 (patch)
tree8a38c80e56524520f61866b84e4370933fc6ddba
parent1dc5df2b7517f8fb7446172c2f6490258f0afba4 (diff)
parent9f2ee9b7ecd91b0a2c75d0bcf1a28be02c880797 (diff)
downloadotp-a8ba18249d6fd3a913f320bdeeb8b9ea5eef2888.tar.gz
otp-a8ba18249d6fd3a913f320bdeeb8b9ea5eef2888.tar.bz2
otp-a8ba18249d6fd3a913f320bdeeb8b9ea5eef2888.zip
Merge branch 'sverker/erts/hipe-arm-freebsd-clear-cache/ERL-958' into maint
OTP-15874 PR-2266 * sverker/erts/hipe-arm-freebsd-clear-cache/ERL-958: erts: Fix hipe_flush_icache_range for FreeBSD on ARM
-rw-r--r--erts/emulator/hipe/hipe_arm.c23
1 files changed, 19 insertions, 4 deletions
diff --git a/erts/emulator/hipe/hipe_arm.c b/erts/emulator/hipe/hipe_arm.c
index b61939724c..c5e2af0b5e 100644
--- a/erts/emulator/hipe/hipe_arm.c
+++ b/erts/emulator/hipe/hipe_arm.c
@@ -30,24 +30,39 @@
#include "hipe_native_bif.h" /* nbif_callemu() */
#include "hipe_bif0.h"
+#ifndef __has_builtin
+# define __has_builtin(x) 0
+#endif
+
/* Flush dcache and invalidate icache for a range of addresses. */
void hipe_flush_icache_range(void *address, unsigned int nbytes)
{
-#if defined(__ARM_EABI__)
+ void* end = (char*)address + nbytes;
+
+#if ERTS_AT_LEAST_GCC_VSN__(4, 3, 0) || __has_builtin(__builtin___clear_cache)
+ __builtin___clear_cache(address, end);
+#elif defined(__clang__)
+ void __clear_cache(void *start, void *end);
+ __clear_cache(address, end);
+#elif defined(__linux__)
+# if defined(__ARM_EABI__)
register unsigned long beg __asm__("r0") = (unsigned long)address;
- register unsigned long end __asm__("r1") = (unsigned long)address + nbytes;
+ register unsigned long end __asm__("r1") = (unsigned long)end;
register unsigned long flg __asm__("r2") = 0;
register unsigned long scno __asm__("r7") = 0xf0002;
__asm__ __volatile__("swi 0" /* sys_cacheflush() */
: "=r"(beg)
: "0"(beg), "r"(end), "r"(flg), "r"(scno));
-#else
+# else
register unsigned long beg __asm__("r0") = (unsigned long)address;
- register unsigned long end __asm__("r1") = (unsigned long)address + nbytes;
+ register unsigned long end __asm__("r1") = (unsigned long)end;
register unsigned long flg __asm__("r2") = 0;
__asm__ __volatile__("swi 0x9f0002" /* sys_cacheflush() */
: "=r"(beg)
: "0"(beg), "r"(end), "r"(flg));
+# endif
+#else
+# error "Don't know how to flush instruction cache"
#endif
}