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author | Lukas Larsson <[email protected]> | 2018-07-07 11:33:54 +0200 |
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committer | Björn Gustavsson <[email protected]> | 2019-04-04 12:30:20 +0200 |
commit | fa9e189d90a35f2ce4b7fc145c994828f34b3548 (patch) | |
tree | 8031ef661e551a2e4e557f3401b6a857293e7fa9 /erts/emulator/internal_doc/PTables.md | |
parent | 0a8bb0bc0a33ddd100278f35460cdfaffa7c15ae (diff) | |
download | otp-fa9e189d90a35f2ce4b7fc145c994828f34b3548.tar.gz otp-fa9e189d90a35f2ce4b7fc145c994828f34b3548.tar.bz2 otp-fa9e189d90a35f2ce4b7fc145c994828f34b3548.zip |
erl_docgen: Add new internal docs chapter to docs
Diffstat (limited to 'erts/emulator/internal_doc/PTables.md')
-rw-r--r-- | erts/emulator/internal_doc/PTables.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/erts/emulator/internal_doc/PTables.md b/erts/emulator/internal_doc/PTables.md index 6fe0e7665d..ef61963a40 100644 --- a/erts/emulator/internal_doc/PTables.md +++ b/erts/emulator/internal_doc/PTables.md @@ -85,13 +85,13 @@ following: 3. Depending on use, issue appropriate memory barrier. A common barrier used is a barrier with acquire semantics. On - x86/x86_64 this maps to a compiler barrier preventing the compiler + x86/x86\_64 this maps to a compiler barrier preventing the compiler to reorder instructions, but on other hardware often some kind of light weight hardware memory barrier is also needed. When comparing with a locked approach, at least one heavy weight memory barrier will be issued when locking the lock on most, if - not all, hardware architectures (including x86/x86_64), and often + not all, hardware architectures (including x86/x86\_64), and often some kind of light weight memory barrier will be issued when unlocking the lock. |