Merge margnus1/hipe-range-split-rebase/PR-1380/OTP-14293

HiPE: Range splitting register allocation

1 files changed, 15 insertions, 2 deletions

diff --git a/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl b/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
index 8a3ea92156..891c874a15 100644
--- a/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
+++ b/lib/hipe/amd64/hipe_amd64_ra_sse2_postconditions.erl
@@ -53,6 +53,8 @@ do_insn(I, TempMap, Strategy) ->	% Insn -> {Insn list, DidSpill}
       do_fp_unop(I, TempMap, Strategy);
     #fp_binop{} ->
       do_fp_binop(I, TempMap, Strategy);
+    #pseudo_spill_fmove{} ->
+      do_pseudo_spill_fmove(I, TempMap, Strategy);
     _ ->
       %% All non sse2 ops
       {[I], false}
@@ -95,8 +97,13 @@ do_fmove(I, TempMap, Strategy) ->
   of
     true ->
       Tmp = spill_temp(double, Strategy),
-      {[#fmove{src=Src, dst=Tmp},I#fmove{src=Tmp,dst=Dst}],
-       true};
+      %% pseudo_spill_fmove allows spill slot move coalescing, but must not
+      %% contain memory operands (except for spilled temps)
+      Is = case is_float_temp(Src) andalso is_float_temp(Dst) of
+	     true -> [#pseudo_spill_fmove{src=Src, temp=Tmp, dst=Dst}];
+	     false -> [#fmove{src=Src, dst=Tmp},I#fmove{src=Tmp,dst=Dst}]
+	   end,
+      {Is, true};
     false ->
       {[I], false}
   end.
@@ -104,6 +111,12 @@ do_fmove(I, TempMap, Strategy) ->
 is_float_temp(#x86_temp{type=Type}) -> Type =:= double;
 is_float_temp(#x86_mem{}) -> false.
 
+%%% Fix an pseudo_spill_fmove op.
+do_pseudo_spill_fmove(I = #pseudo_spill_fmove{temp=Temp}, TempMap, _Strategy) ->
+  %% Temp is above the low water mark and must not have been spilled
+  false = is_mem_opnd(Temp, TempMap),
+  {[I], false}. % nothing to do
+
 %%% Check if an operand denotes a memory cell (mem or pseudo).
 
 is_mem_opnd(Opnd, TempMap) ->