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authorMagnus Lång <[email protected]>2017-03-16 15:30:00 +0100
committerMagnus Lång <[email protected]>2017-03-16 20:49:42 +0100
commitc52b2cf226cb3f1bb1b16bee28d47785506adff3 (patch)
treef016829f93e26db7fe7e2329ace868f4b2442510 /lib/hipe/arm/hipe_arm_subst.erl
parentd1d26f4bf9da3cc5eab4e918df771d67fe9e6bb5 (diff)
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hipe: Add pseudo_spill_f?move instructions
These pseudo instructions are added to all backends and allow spill slot to spill slot move coalescing in a clean way. They have regular move semantics, but contain an additional scratch register to be used if both source and destination are spilled, and can not be move coalesced. Additionally, a register allocator callback Target:is_spill_move(Instr, Context) is added which allows the spill slot allocators to check for these instructions and try to coalesce the spill slots the two temporaries are allocated to.
Diffstat (limited to 'lib/hipe/arm/hipe_arm_subst.erl')
-rw-r--r--lib/hipe/arm/hipe_arm_subst.erl2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/hipe/arm/hipe_arm_subst.erl b/lib/hipe/arm/hipe_arm_subst.erl
index a41a907a4c..4ff245f414 100644
--- a/lib/hipe/arm/hipe_arm_subst.erl
+++ b/lib/hipe/arm/hipe_arm_subst.erl
@@ -59,6 +59,8 @@ insn_temps(T, I) ->
#pseudo_call{funv=F} -> I#pseudo_call{funv=funv_temps(T, F)};
#pseudo_call_prepare{} -> I;
#pseudo_li{dst=D} -> I#pseudo_li{dst=T(D)};
+ #pseudo_spill_move{dst=D,temp=U,src=S} ->
+ I#pseudo_spill_move{dst=T(D),temp=T(U),src=T(S)};
#pseudo_switch{jtab=J=#arm_temp{},index=Ix=#arm_temp{}} ->
I#pseudo_switch{jtab=T(J),index=T(Ix)};
#pseudo_tailcall{funv=F,stkargs=Stk} ->